From 27830d0ec375e49e7e0cb4e26bbc03ea5c3d5a84 Mon Sep 17 00:00:00 2001 From: Shon Wang Date: Fri, 28 Jul 2023 11:27:32 +0800 Subject: mb/google/brya/var/vell: Disable PCH USB2 phy power gating The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for vell board. Please refer Intel doc#723158 for more information. BUG=b:293535284 TEST=build and boot vell Change-Id: I8a4d633fbd362188aedef373e515c7bfe5c4327a Signed-off-by: Shon Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/76770 Tested-by: build bot (Jenkins) Reviewed-by: Derek Huang Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/vell/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 5298a7e3582f..c024796e62f3 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -71,6 +71,10 @@ chip soc/intel/alderlake register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" register "sagv" = "SaGv_Enabled" + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "usb2_phy_sus_pg_disable" = "1" + # Set EPP to 50%: 50 * 256 / 100 = 0x80 register "enable_energy_perf_pref" = "true" register "energy_perf_pref_value" = "0x80" -- cgit v1.2.3