From 2437fe9dfab8e4056b633a39d51d07aa81ab3c9d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 4 Oct 2019 13:59:29 +0200 Subject: sb/intel/i82801gx: Move CIR init to a common place Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too. Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/intel/d945gclf/romstage.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) (limited to 'src/mainboard/intel/d945gclf/romstage.c') diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index bad2b6d5388a..f6fc8df2f43f 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -89,31 +89,7 @@ static void early_ich7_init(void) reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; + ich7_setup_cir(); } void mainboard_romstage_entry(void) -- cgit v1.2.3