From e9b937352eec6e5e5b4a7e120f77f15a2732ac03 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 17 Sep 2020 15:48:54 +0530 Subject: apollolake boards: Enable CSE in devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let Intel common cse block code can use this device. Calling me_read_config32(offset) function from ramstage: Without this CL : HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL! With this CL : HECI: Global Reset(Type:1) Command HECI: Global Reset success! Signed-off-by: Subrata Banik Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/mainboard/intel/minnow3/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/intel/minnow3') diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index 6c872b186e88..e2f2f8e5599c 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - PCIe-A 0 -- cgit v1.2.3