From 8a18bd8500fee7c43e257d3dfd1cc3f7db82c88c Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 9 Jun 2021 21:57:49 +0530 Subject: soc/intel/alderlake/romstage: Update display UPDs based on InternalGfx Disable all display related UPDs if IGD is not enabled as FSP don't need to perform display port initialization while IGD itself is disabled else assign UPDs based on devicetree config. TEST=Dump FSP-M display related UPDs with IGD enable and disable to ensure patch integrity. Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/adlrvp/devicetree.cb | 5 +++-- src/mainboard/intel/adlrvp/devicetree_m.cb | 5 +++-- .../variants/baseboard/devicetree.cb | 22 +++++++--------------- 3 files changed, 13 insertions(+), 19 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index ad7c971f0d75..be2659293f34 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -125,8 +125,9 @@ chip soc/intel/alderlake # Enable EDP in PortA register "DdiPortAConfig" = "1" # Enable HDMI in Port B - register "DdiPortBDdc" = "1" - register "DdiPortBHpd" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" # TCSS USB3 register "TcssAuxOri" = "0" diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index f6bd0f35aef9..ae248429a9d0 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -82,8 +82,9 @@ chip soc/intel/alderlake # Enable EDP in PortA register "DdiPortAConfig" = "1" # Enable HDMI in Port B - register "DdiPortBDdc" = "1" - register "DdiPortBHpd" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" # TCSS USB3 register "TcssAuxOri" = "0" diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 5b6a09710d8a..d5e5951c2a5c 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -118,21 +118,13 @@ chip soc/intel/alderlake register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" - register "DdiPortAHpd" = "1" - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "0" - register "DdiPort1Hpd" = "1" - register "DdiPort2Hpd" = "1" - register "DdiPort3Hpd" = "0" - register "DdiPort4Hpd" = "0" - - register "DdiPortADdc" = "0" - register "DdiPortBDdc" = "1" - register "DdiPortCDdc" = "0" - register "DdiPort1Ddc" = "0" - register "DdiPort2Ddc" = "0" - register "DdiPort3Ddc" = "0" - register "DdiPort4Ddc" = "0" + # Enable Display Port Configuration + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD, + }" # Intel Common SoC Config #+-------------------+---------------------------+ -- cgit v1.2.3