From aa49608a2bf474355f0a7cf767e10326259254ed Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Fri, 7 May 2021 20:11:53 +0530 Subject: soc/intel/adl: Add SKU specific power limits support Power limits (PL1 and PL2) depend on the specific SKU of the CPU. By expanding the SoC chip config power_limits_config member to an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the appropriate power limits are applied. Using this the correct set of power limits are being selected from the array based on system agent PCI ID. Based on this, chipset.cb file contains the set of power limits being used by varieties of ADL boards. These power limit values are as per document 619501. BUG=None BRANCH=None TEST=Built and verified the following console output on below boards On adlrvp (482): CPU PL1 = 28 Watts CPU PL2 = 64 Watts On adlrvp (682): CPU PL1 = 45 Watts CPU PL2 = 115 Watts On brya (282): CPU PL1 = 15 Watts CPU PL2 = 55 Watts Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Selma Bensaid --- src/mainboard/intel/adlrvp/devicetree.cb | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 9def4be7d32b..ad7c971f0d75 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -134,11 +134,6 @@ chip soc/intel/alderlake register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "power_limits_config" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 56, - }" - register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, -- cgit v1.2.3