From 72628fa813231cb5af6a5aa373e184d2fd8a9509 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Mon, 22 Nov 2021 02:51:14 +0300 Subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads It was already enabled on T520 and L520, but disabled on X220, T420 and T420s. On X220, it was disabled by commit 0793afe9 (mb/lenovo/x220: disable ME). I can't reproduce those issues today on linux 4.4 and linux 5.13. Also, it breaks the me_disable feature, we already have a Kconfig option to hide MEI in case of errors, and it will be hidden on disabled, recovery, firmware update paths anyway. Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/59527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Alexander Couzens --- src/mainboard/lenovo/t420/devicetree.cb | 2 +- src/mainboard/lenovo/t420s/devicetree.cb | 2 +- src/mainboard/lenovo/x220/devicetree.cb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/lenovo') diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index e42e519f87b2..457ccbee1bee 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -61,7 +61,7 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index ab98ca0bd0b6..32736a83f2c8 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -63,7 +63,7 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 53eb23a1bd51..b239d64daec4 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -60,7 +60,7 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT -- cgit v1.2.3