From 57779955c9be64426e591557fe8571637028ddad Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 19 May 2022 15:35:31 +0100 Subject: soc/intel/apollolake: Hook Up SataPortEnable to devicetree Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb') diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 6c17d6329870..f1594d2b7748 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -71,6 +71,8 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 -- cgit v1.2.3