From 08d304f05b1a1871014bf149c1982985b0feed87 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 25 Aug 2021 09:42:50 +0200 Subject: mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason, we have to adjust the PIR8 register (0x3150) which is responsible for PCIe device 25h. The bridge is connected to PCIe root port 7. The following routing is required: INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# TEST: - Boot into system software Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc | 1 + src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c (limited to 'src/mainboard/siemens/mc_ehl') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc index 9cb0f1d4d4f2..2903dd1ac046 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += mainboard.c SPD_SOURCES = mc_ehl2 # 0b000 LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c new file mode 100644 index 000000000000..4ae857c69ab7 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void variant_mainboard_final(void) +{ + /* PIR8 register mapping for PCIe root ports + INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */ + pcr_write16(PID_ITSS, 0x3150, 0x1032); +} -- cgit v1.2.3