From fb4fdac64cfe05c9642cd93129dbbf23dde4ac51 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Fri, 17 Mar 2023 10:02:54 +0100 Subject: mb/siemens/mc_ehl4: Limit PCIe root port #4 and #5 speed to Gen 1 Due to a non-optimal RX signal (receive) on PCIe root port #4 (00:1c.3) and #5 (00:1c.4), the speed must be limit to Gen 1. BUG=none TEST=RX signal measured with oscilloscope Change-Id: I695c0ef961290676fe421b6efd631d6e94d6d556 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/73767 Reviewed-by: Jan Samek Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan Reviewed-by: Maximilian Brune --- src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/siemens') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index 1bf99fd8377e..52da98e2e276 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -74,6 +74,10 @@ chip soc/intel/elkhartlake register "PcieRpLtrDisable[3]" = "true" register "PcieRpLtrDisable[4]" = "true" + # Determines PCIe root port speed + register "PcieRpPcieSpeed[3]" = "1" + register "PcieRpPcieSpeed[4]" = "1" + # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" -- cgit v1.2.3