From ad50b40eed3f7f235e848a2382ffbee6a51d1755 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 3 Jan 2022 19:12:55 +0000 Subject: soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` config List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/system76/galp5/devicetree.cb | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/mainboard/system76/galp5/devicetree.cb') diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 716afd4d0a22..8bc74e34e151 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -253,9 +253,7 @@ chip soc/intel/tigerlake # TODO: Pantone ROM? register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" -- cgit v1.2.3