From 3ee18cefa3e8a33720e9f62c4034f9fa76789105 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 20 Jul 2021 12:48:12 +0200 Subject: mb/siemens/mc_ehl1: Adjust USB port settings in devicetree There are in total three USB ports that are used on mc_ehl1: - Port 1: Type A connector connected to USB2/USB3 port 0 - Port 2: Type A connector connected to USB2/USB3 port 1 - Onboard: connected to USB2 port 2 None of the ports supports overcurrent reporting. Adjust the appropriate UPDs in devicetree to match the hardware configuration. Change-Id: I220637b8e9f03efccacd0955e82cfc0c7a6f53ee Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/56454 Reviewed-by: Mario Scheithauer Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 30 +++++++++++----------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 1c48c99c8a93..ec0fe5ac87c6 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -21,21 +21,21 @@ chip soc/intel/elkhartlake register "Heci2Enable" = "1" # USB related UPDs - register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # USB2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-C Port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port4 - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # UNUSED + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Port is unused + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Port is not used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Port is not used # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" -- cgit v1.2.3