From d99de5db5b9e46fd2595c0946cad9bb6da9b2b8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 3 Apr 2023 13:25:17 +0200 Subject: mainboard/protectli/vault_cml: Switch to IT8784E MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The first platform samples came with IT8786E. The production units switched to IT8784E in the final design. Change the code to use IT8784E and reflect the proprietary firmware configuration of the SIO chip. TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the configuration with superiotool and compare the configuration with proprietary firmware. Signed-off-by: Michał Żygowski Change-Id: I5dc6669b592484e445c8c4bbe95d73f0a9f0392e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74175 Reviewed-by: Martin L Roth Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/mainboard/protectli/vault_cml/Kconfig | 2 +- src/mainboard/protectli/vault_cml/acpi/superio.asl | 13 +++++++++++++ src/mainboard/protectli/vault_cml/bootblock.c | 8 ++++---- src/mainboard/protectli/vault_cml/devicetree.cb | 20 +++++++------------- src/mainboard/protectli/vault_cml/dsdt.asl | 5 +++++ 5 files changed, 30 insertions(+), 18 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/protectli/vault_cml/Kconfig b/src/mainboard/protectli/vault_cml/Kconfig index 6e7136d6f268..fa6606343d50 100644 --- a/src/mainboard/protectli/vault_cml/Kconfig +++ b/src/mainboard/protectli/vault_cml/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_COMETLAKE_2 if BOARD_PROTECTLI_VP4630_VP4650 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPI_FLASH_MACRONIX - select SUPERIO_ITE_IT8786E + select SUPERIO_ITE_IT8784E config MAINBOARD_DIR default "protectli/vault_cml" diff --git a/src/mainboard/protectli/vault_cml/acpi/superio.asl b/src/mainboard/protectli/vault_cml/acpi/superio.asl index 853b0877b33d..f5c9191a3e3c 100644 --- a/src/mainboard/protectli/vault_cml/acpi/superio.asl +++ b/src/mainboard/protectli/vault_cml/acpi/superio.asl @@ -1 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8784E_SHOW_UARTA +#undef IT8784E_SHOW_UARTB +#undef IT8784E_SHOW_EC +#undef IT8784E_SHOW_KBC +#undef IT8784E_SHOW_PS2M +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8784E_SHOW_SP1 +#define IT8784E_SHOW_EC +#include diff --git a/src/mainboard/protectli/vault_cml/bootblock.c b/src/mainboard/protectli/vault_cml/bootblock.c index 9052fb8631c7..82c46f985f38 100644 --- a/src/mainboard/protectli/vault_cml/bootblock.c +++ b/src/mainboard/protectli/vault_cml/bootblock.c @@ -3,18 +3,18 @@ #include #include #include -#include +#include #include "gpio.h" -#define UART_DEV PNP_DEV(0x2e, IT8786E_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8786E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8784E_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8784E_GPIO) void bootblock_mainboard_early_init(void) { /* CLKIN freq 24MHz, Ext CLKIN for Watchdog, Internal VCC_OK */ ite_reg_write(GPIO_DEV, 0x23, 0x49); /* Set pin native functions */ - ite_reg_write(GPIO_DEV, 0x26, 0x00); + ite_reg_write(GPIO_DEV, 0x26, 0xf3); /* Set GPIOS exposed on pin header as GPIO functions */ ite_reg_write(GPIO_DEV, 0x29, 0xc0); /* External CLKIN PCICLK */ diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 154d81a4a9e9..3ba2b0198dbe 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -192,17 +192,17 @@ chip soc/intel/cannonlake device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on - chip superio/ite/it8786e - register "TMPIN1.mode" = "THERMAL_PECI" - register "TMPIN1.offset" = "0x63" + chip superio/ite/it8784e + register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_MODE_DISABLED" - register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" + register "TMPIN3.mode" = "THERMAL_PECI" + register "TMPIN3.offset" = "0x63" register "ec.vin_mask" = "VIN_ALL" register "ec.smbus_24mhz" = "1" register "ec.smbus_en" = "1" # FAN1 is CPU fan (connector on board) register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = " 1" + register "FAN1.smart.tmpin" = " 3" register "FAN1.smart.tmp_off" = "40" register "FAN1.smart.tmp_start" = "60" register "FAN1.smart.tmp_full" = "85" @@ -215,24 +215,18 @@ chip soc/intel/cannonlake io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on # COM 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end + device pnp 2e.2 on end # COM 2 device pnp 2e.3 off end # Printer Port device pnp 2e.4 on # Environment Controller io 0x60 = 0xa40 io 0x62 = 0xa30 irq 0x70 = 9 + irq 0xf0 = 0x80 # clear 3VSB status end device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # Mouse device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # COM 3 - device pnp 2e.9 off end # COM 4 device pnp 2e.a off end # CIR - device pnp 2e.b off end # COM 5 - device pnp 2e.c off end # COM 6 end chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/protectli/vault_cml/dsdt.asl b/src/mainboard/protectli/vault_cml/dsdt.asl index cb0922a5ea2e..8240fc94155f 100644 --- a/src/mainboard/protectli/vault_cml/dsdt.asl +++ b/src/mainboard/protectli/vault_cml/dsdt.asl @@ -21,5 +21,10 @@ DefinitionBlock( #include } + Scope (\_SB.PCI0.LPCB) + { + #include "acpi/superio.asl" + } + #include } -- cgit v1.2.3