From eac687cc36823683b80ab21e43038a42bf90921c Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 22 Jul 2021 13:49:36 +0200 Subject: mb/siemens/mc_ehl1: Add GPIO configuration Provide a valid GPIO configuration based on the mainboard wiring. Change-Id: I36f0e8292a405b4bac74fbc5fde62e5e414387e7 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/56519 Reviewed-by: Mario Scheithauer Tested-by: build bot (Jenkins) --- .../siemens/mc_ehl/variants/mc_ehl1/gpio.c | 410 ++++++++------------- 1 file changed, 154 insertions(+), 256 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c index 9d17c80d3fcb..91c041756fb2 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c @@ -5,266 +5,164 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { -/*BT_RF_KILL_N*/ -PAD_CFG_GPO(GPP_E11, 1, DEEP), - -/*WIFI_RF_KILL_N*/ -PAD_CFG_GPO(GPP_E10, 1, DEEP), - -/*M.2_WLAN_PERST_N*/ -PAD_CFG_GPO(GPD7, 1, PLTRST), - -/*M.2_WLAN_SLP*/ -PAD_CFG_GPO(GPD9, 1, PLTRST), - -/*WIFI_WAKE_N*/ -PAD_CFG_GPI_SCI(GPP_F4, UP_5K, DEEP, LEVEL, INVERT), - -/*UART_BT_WAKE_N*/ -PAD_CFG_GPI_SCI(GPP_F20, NONE, DEEP, LEVEL, INVERT), - -/*ONBOARD_X4_PCIE_SLOT1_RESET_N*/ -PAD_CFG_GPO(GPD11, 1, PLTRST), - -/*ONBOARD_X4_PCIE_SLOT1_WAKE_N*/ -PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), - -/*M.2_WWAN_PWR_EN*/ -PAD_CFG_GPO(GPP_F21, 1, PLTRST), - -/*M.2_WWAN_RST_N*/ -PAD_CFG_GPO(GPP_V13, 1, PLTRST), - -/*M.2_WWAN_PE_RST_N*/ -PAD_CFG_GPO(GPP_B14, 1, PLTRST), - -/*M.2_WWAN_PE_WAKE_N*/ -PAD_CFG_GPO(GPP_B17, 1, PLTRST), - -/*M.2_WWAN_FCP_OFF_N*/ -PAD_CFG_GPO(GPP_E0, 1, PLTRST), - -/*M.2_SSD_SATA_DEVSLP_1*/ -PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), - -/*BC_PROCHOT_N*/ -PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), - -/*FPS_RST_N*/ -PAD_CFG_GPO(GPP_V14, 1, PLTRST), - -/*FPS_INT*/ -PAD_CFG_GPI_APIC(GPP_V15, NONE, PLTRST, LEVEL, NONE), - -/*CODEC_INT_N*/ -PAD_CFG_GPI(GPP_B15, NONE, PLTRST), - -/*TCH_PNL_PWR_EN*/ -PAD_CFG_GPO(GPP_B16, 1, PLTRST), - -/*THC0_SPI1_INT_N*/ -PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, INVERT), - -/*SPI_TPM_INT_N*/ -PAD_CFG_GPI_APIC(GPP_G19, NONE, DEEP, LEVEL, NONE), - -/*EMMC_CMD*/ -PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), - -/*EMMC_DATA0*/ -PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), - -/*EMMC_DATA1*/ -PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), - -/*EMMC_DATA2*/ -PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), - -/*EMMC_DATA3*/ -PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), - -/*EMMC_DATA4*/ -PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), - -/*EMMC_DATA5*/ -PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), - -/*EMMC_DATA6*/ -PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), - -/*EMMC_DATA7*/ -PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), - -/*EMMC_RCLK*/ -PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), - -/*EMMC_CLK*/ -PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), - -/*EMMC_RESET*/ -PAD_CFG_NF(GPP_V11, UP_20K, DEEP, NF1), - -/*ACPRESENT*/ -PAD_CFG_NF(GPD1, NONE, PLTRST, NF1), - -/*RGMII0_MDC*/ -PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - -/*RGMII0_MDIO*/ -PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - -/*RGMII0_INT*/ -PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), - -/*RGMII0_RESETB*/ -PAD_CFG_GPO(GPP_T5, 1, DEEP), - -/*RGMII0_AUXTS*/ -PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), - -/*RGMII0_PPS*/ -PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - -/*RGMII1_MDC*/ -PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), - -/*RGMII1_MDIO*/ -PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), - -/*RGMII1_INT*/ -PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), - -/*RGMII1_RESETB*/ -PAD_CFG_GPO(GPP_H1, 1, DEEP), - -/*RGMII1_AUXTS*/ -PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), - -/*RGMII1_PPS*/ -PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), - -/*RGMII2_MDC*/ -PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - -/*RGMII2_MDIO*/ -PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - -/*RGMII2_INT*/ -PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1), - -/*RGMII2_RESETB*/ -PAD_CFG_GPO(GPP_U1, 1, DEEP), + /* Community 0 - GpioGroup GPP_B */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */ + PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */ + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF4), /* ESPI_ALERT1_N */ + PAD_NC(GPP_B9, NONE), /* Not connected */ + PAD_NC(GPP_B10, NONE), /* Not connected */ + PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */ + PAD_NC(GPP_B14, NONE), /* Not connected */ + PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5), /* ESPI_CS1_N */ + PAD_NC(GPP_B18, NONE), /* Not connected */ + PAD_NC(GPP_B19, NONE), /* Not connected */ + PAD_NC(GPP_B20, NONE), /* Not connected */ + PAD_NC(GPP_B21, NONE), /* Not connected */ + PAD_NC(GPP_B22, NONE), /* Not connected */ + PAD_NC(GPP_B23, NONE), /* Not connected */ + + /* Community 0 - GpioGroup GPP_T */ + PAD_CFG_NF(GPP_T4, UP_20K, DEEP, NF1), /* PSE_GBE0_INT */ + PAD_CFG_NF(GPP_T5, DN_20K, DEEP, NF1), /* PSE_GBE0_RST_N */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */ + + /* Community 0 - GpioGroup GPP_G */ + PAD_NC(GPP_G8, NONE), /* Not connected */ + PAD_NC(GPP_G9, NONE), /* Not connected */ + PAD_NC(GPP_G12, NONE), /* Not connected */ + PAD_CFG_NF(GPP_G15, NONE, DEEP, NF1), /* ESPI_IO_0 */ + PAD_CFG_NF(GPP_G16, NONE, DEEP, NF1), /* ESPI_IO_1 */ + PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* ESPI_IO_2 */ + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* ESPI_IO_3 */ + PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */ + PAD_CFG_NF(GPP_G20, NONE, DEEP, NF1), /* ESPI_CSO_N */ + PAD_CFG_NF(GPP_G21, NONE, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1), /* ESPI_RST0_N */ + + /* Community 1 - GpioGroup GPP_V */ + PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET_N */ + + /* Community 1 - GpioGroup GPP_H */ + PAD_CFG_NF(GPP_H0, DN_20K, DEEP, NF1), /* PSE_GBE1_INT */ + PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF1), /* PSE_GBE1_RST_N */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */ + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */ + PAD_CFG_NF(GPP_H8, UP_20K, DEEP, NF1), /* SIO_I2C4_SDA */ + PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1), /* SIO_I2C4_SCL */ + + /* Community 1 - GpioGroup GPP_D */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* EMMC_PWR_EN_N */ + + /* Community 1 - GpioGroup GPP_U */ + PAD_CFG_NF(GPP_U0, DN_20K, DEEP, NF1), /* GBE_INT */ + PAD_CFG_NF(GPP_U1, DN_20K, DEEP, NF1), /* GBE_RST_N */ + PAD_CFG_NF(GPP_U2, NONE, DEEP, NF1), /* GBE_PPS */ + PAD_CFG_NF(GPP_U3, NONE, DEEP, NF1), /* GBE_AUXTS */ + PAD_NC(GPP_U12, NONE), /* Not connected */ + PAD_NC(GPP_U13, NONE), /* Not connected */ + PAD_NC(GPP_U16, NONE), /* Not connected */ + PAD_NC(GPP_U17, NONE), /* Not connected */ + PAD_NC(GPP_U18, NONE), /* Not connected */ + PAD_CFG_GPO(GPP_U19, 1, DEEP), /* UPD_REQ_N */ + + /* Community 2 - GpioGroup DSW */ + PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), /* SLP_S3 */ + PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), /* SLP_S4 */ + PAD_NC(GPD7, NONE), /* Not connected */ + PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), /* SLP_S5 */ + + /* Community 3 - GpioGroup GPP_S */ + PAD_NC(GPP_S0, NONE), /* Not connected */ + PAD_NC(GPP_S1, NONE), /* Not connected */ + + /* Community 3 - GpioGroup GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */ + + /* Community 4 - GpioGroup GPP_C */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */ + PAD_NC(GPP_C5, NONE), /* Not connected */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ + PAD_NC(GPP_C8, NONE), /* Not connected */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF4), /* SIO_I2C1_SDA */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF4), /* SIO_I2C1_SCL */ + + /* Community 4 - GpioGroup GPP_F */ + PAD_NC(GPP_F0, NONE), /* Not connected */ + PAD_NC(GPP_F1, NONE), /* Not connected */ + PAD_NC(GPP_F2, NONE), /* Not connected */ + PAD_NC(GPP_F3, NONE), /* Not connected */ + PAD_NC(GPP_F4, NONE), /* Not connected */ + PAD_NC(GPP_F5, NONE), /* Not connected */ + PAD_NC(GPP_F7, NONE), /* Not connected */ + PAD_NC(GPP_F8, NONE), /* Not connected */ + PAD_NC(GPP_F10, NONE), /* Not connected */ + PAD_NC(GPP_F11, NONE), /* Not connected */ + PAD_NC(GPP_F12, NONE), /* Not connected */ + PAD_NC(GPP_F13, NONE), /* Not connected */ + PAD_NC(GPP_F14, NONE), /* Not connected */ + PAD_NC(GPP_F15, NONE), /* Not connected */ + PAD_NC(GPP_F16, NONE), /* Not connected */ + PAD_NC(GPP_F17, NONE), /* Not connected */ + PAD_NC(GPP_F20, NONE), /* Not connected */ + PAD_NC(GPP_F21, NONE), /* Not connected */ + + /* Community 4 - GpioGroup GPP_E */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */ + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* DDI1_HPD */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DDI1_DDC_SDA */ + PAD_NC(GPP_E6, NONE), /* Not connected */ + PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), /* DDI1_DDC_SCL */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */ + PAD_NC(GPP_E15, NONE), /* Not connected */ + PAD_NC(GPP_E16, NONE), /* Not connected */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDI0_DDC_SDA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */ + PAD_NC(GPP_E23, NONE), /* Not connected */ + + /* Community 5 - GpioGroup GPP_R */ + PAD_NC(GPP_R1, NONE), /* Not connected */ + PAD_NC(GPP_R2, NONE), /* Not connected */ + PAD_NC(GPP_R3, NONE), /* Not connected */ }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* UART1 RX */ -PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), - -/* UART1 TX */ -PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), - -/* UART2 RX */ -PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), - -/* UART2 TX */ -PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), - -/*WWAN_FCP_OFF_N*/ -PAD_CFG_GPO(GPP_E0, 1, PLTRST), - -/*WWAN_PWREN*/ -PAD_CFG_GPO(GPP_F21, 1, PLTRST), - -/*WWAN_PERST_N*/ -PAD_CFG_GPO(GPP_B14, 0, PLTRST), - -/*WWAN_RST_N*/ -PAD_CFG_GPO(GPP_V13, 0, PLTRST), - -/* LAN_WAKEB*/ -PAD_CFG_GPI_SCI(GPD2, NONE, DEEP, EDGE_SINGLE, INVERT), - -/*WWAN_RST_N*/ -PAD_CFG_GPO(GPP_V13, 0, PWROK), - -/*WWAN_PERST_N*/ -PAD_CFG_GPO(GPP_B14, 0, PWROK), - -/*WWAN_FCP_OFF_N*/ -PAD_CFG_GPO(GPP_E0, 0, PWROK), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF2), /* SMB_ALERT_N */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), /* SIO_UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), /* SIO_UART2_TXD */ }; const struct pad_config *variant_gpio_table(size_t *num) -- cgit v1.2.3