From e39becf5216419fa0a08c1d8632474fd8a9a5738 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 5 Jul 2019 18:05:17 +0300
Subject: intel/cpu: Switch older models to TSC_MONOTONIC_TIMER
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The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.

Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/fsp_rangeley/Makefile.inc | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src/northbridge/intel/fsp_rangeley/Makefile.inc')

diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc
index a2f80546d7cc..a167c2369e64 100644
--- a/src/northbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc
@@ -27,8 +27,6 @@ romstage-y += memmap.c
 romstage-y += ../../../arch/x86/walkcbfs.S
 romstage-y += port_access.c
 
-smm-y += udelay.c
-
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)
 
 CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/
-- 
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