From 3eeefba6a0b1be97b5de70ab9d485f8383472f15 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 14 Jun 2021 09:23:40 +0200 Subject: nb/intel/haswell/memmap.h: Define MMIO window sizes Add defines for the sizes of northbridge MMIO windows and use them where applicable. The macro names have been taken from Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I845cba8acbd478cd325d2e364138336d985f9c34 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/55479 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/haswell/northbridge.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'src/northbridge/intel/haswell/northbridge.c') diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index fdaac7c311a1..02799d3f1183 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -85,15 +85,13 @@ struct fixed_mmio_descriptor { const char *description; }; -#define SIZE_KB(x) ((x) * 1024) struct fixed_mmio_descriptor mc_fixed_resources[] = { - { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, - { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, - { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, - { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, + { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, + { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, + { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, + { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, }; -#undef SIZE_KB /* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ static void mc_add_fixed_mmio_resources(struct device *dev) -- cgit v1.2.3