From ad787e18e0ed24495132d0e9e638ed835afad354 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Mon, 30 Sep 2019 04:14:19 +0300
Subject: intel/i945,i82801gx: Refactor early PCI bridge reset
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Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/i945/i945.h | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src/northbridge/intel/i945/i945.h')

diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index d19748eaf9e0..69a6413f42fb 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -83,8 +83,6 @@
 /* Device 0:1.0 PCI configuration space (PCI Express) */
 
 #define PCISTS1		0x06	/* 16bit */
-#define SBUSN1		0x19	/*  8bit */
-#define SUBUSN1		0x1a	/*  8bit */
 #define SSTS1		0x1e	/* 16bit */
 #define PEG_CAP		0xa2	/* 16bit */
 #define DSTS		0xaa	/* 16bit */
-- 
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