From 0a20872de0b0de6354fa3164c998619b3218dd9f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 18 Sep 2020 00:52:26 +0200 Subject: nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400 The 100 MHz reference clock seems to be unstable when using high multipliers. Use the 133 MHz reference clock instead. Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45503 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_native.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/sandybridge/raminit_native.c') diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 4c1fb8fe1773..698db513bde1 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -218,7 +218,7 @@ static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) { if (ctrl->tCK <= TCK_1200MHZ) { ctrl->tCK = TCK_1200MHZ; - ctrl->base_freq = 100; + ctrl->base_freq = 133; } else if (ctrl->tCK <= TCK_1100MHZ) { ctrl->tCK = TCK_1100MHZ; ctrl->base_freq = 100; -- cgit v1.2.3