From afebab1ebe109c7b9ca9820679a4681b996bce0b Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 18 Nov 2023 18:03:40 +0100 Subject: sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree Since the XHCI controller in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the XHCI device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79170 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/northbridge/intel/sandybridge/chipset.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 9cdb6639b4ff..c304ab4c81ab 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -19,7 +19,7 @@ chip northbridge/intel/sandybridge device pci 06.0 alias peg60 off end # PEG60 chip southbridge/intel/bd82x6x # Intel Series 6/7 PCH - device pci 14.0 alias xhci off end # USB 3.0 Controller (only on 7 series) + device pci 14.0 alias xhci off ops bd82x6x_usb_xhci_ops end # XHCI Controller only on 7 series device pci 16.0 alias mei1 on end # Management Engine Interface 1 device pci 16.1 alias mei2 off end # Management Engine Interface 2 device pci 16.2 alias me_ide_r off end # Management Engine IDE-R -- cgit v1.2.3