From 187f59accba64e9fbfbe10541a832861efd73202 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Tue, 8 Dec 2020 02:25:05 +0100
Subject: soc/amd/picasso: split southbridge into bootblock and ramstage code

The ramstage parts gets renamed to fch.c and the bootblock one to
early_fch.c. No functionality from the old southbridge file is used in
romstage, so don't link it there.

Change-Id: I7ca3b5238c3b841191dd0459996b691edd76fbf8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/picasso/early_fch.c | 59 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 src/soc/amd/picasso/early_fch.c

(limited to 'src/soc/amd/picasso/early_fch.c')

diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c
new file mode 100644
index 000000000000..f56a7585a444
--- /dev/null
+++ b/src/soc/amd/picasso/early_fch.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/espi.h>
+#include <amdblocks/lpc.h>
+#include <amdblocks/smbus.h>
+#include <amdblocks/spi.h>
+#include <console/console.h>
+#include <soc/i2c.h>
+#include <soc/southbridge.h>
+#include <soc/uart.h>
+#include <types.h>
+
+static void lpc_configure_decodes(void)
+{
+	if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
+		lpc_enable_port80();
+}
+
+/* Before console init */
+void fch_pre_init(void)
+{
+	lpc_early_init();
+
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+		lpc_configure_decodes();
+
+	fch_spi_early_init();
+	enable_acpimmio_decode_pm04();
+	fch_smbus_init();
+	fch_enable_cf9_io();
+	fch_enable_legacy_io();
+	enable_aoac_devices();
+	sb_reset_i2c_slaves();
+
+	/*
+	 * On reset Range_0 defaults to enabled. We want to start with a clean
+	 * slate to not have things unexpectedly enabled.
+	 */
+	clear_uart_legacy_config();
+
+	if (CONFIG(PICASSO_CONSOLE_UART))
+		set_uart_config(CONFIG_UART_FOR_CONSOLE);
+}
+
+/* After console init */
+void fch_early_init(void)
+{
+	fch_print_pmxc0_status();
+	i2c_soc_early_init();
+
+	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
+		lpc_disable_spi_rom_sharing();
+
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+		espi_setup();
+		espi_configure_decodes();
+	}
+}
-- 
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