From 59d64f06be8eb5f80acfb0b53e7accaf05c1bec8 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 6 Dec 2021 14:54:55 -0700 Subject: soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI > only platforms (where SCI_EN is always set), when transitioning from > either the mechanical off (G3) or soft-off state to the G0 working > state this register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/picasso/fch.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/soc/amd/picasso/fch.c') diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 44acc817ef19..03ba914c810b 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -225,8 +225,6 @@ void fch_init(void *chip_info) acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - acpi_clear_pm_gpe_status(); - al2ahb_clock_gate(); gpp_clk_setup(); -- cgit v1.2.3