From 697fa74027402e8eb01c69ee6407599f6cacca75 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 3 Mar 2022 20:54:38 +0100 Subject: soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to clarify that this isn't the address the SPI flash gets mapped, but the address of the SPI controller MMIO region. This also aligns the register name with the PPR. Signed-off-by: Felix Held Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578 Tested-by: build bot (Jenkins) Reviewed-by: Jason Glenesk Reviewed-by: Raul Rangel Reviewed-by: Fred Reitberger --- src/soc/amd/picasso/include/soc/lpc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/include/soc/lpc.h b/src/soc/amd/picasso/include/soc/lpc.h index 2705f2d9e55f..24d12b3b9e05 100644 --- a/src/soc/amd/picasso/include/soc/lpc.h +++ b/src/soc/amd/picasso/include/soc/lpc.h @@ -3,7 +3,7 @@ #ifndef AMD_PICASSO_LPC_H #define AMD_PICASSO_LPC_H -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(8) #define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) #define PSP_SPI_MMIO_SEL BIT(4) -- cgit v1.2.3