From a05f518dea5fe700d99dcce1882739a15427a0d9 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 10 Jun 2022 21:04:36 +0200 Subject: soc/amd/sabrina: only make the available clock outputs configurable Sabrina only has 4 PCIe clock outputs with corresponding clock request pins available, so only make those 4 configurable in devicetree and disable the rest unconditionally. TEST=None Signed-off-by: Felix Held Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Raul Rangel --- src/soc/amd/sabrina/include/soc/southbridge.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/sabrina/include') diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h index e755d5019caf..d72696285d36 100644 --- a/src/soc/amd/sabrina/include/soc/southbridge.h +++ b/src/soc/amd/sabrina/include/soc/southbridge.h @@ -96,6 +96,7 @@ #define GPP_CLK5_REQ_SHIFT 10 #define GPP_CLK6_REQ_SHIFT 12 #define GPP_CLK_OUTPUT_COUNT 7 +#define GPP_CLK_OUTPUT_AVAILABLE 4 #define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) -- cgit v1.2.3