From 07baa7a7f06369d9dc795c5a9b34314e88d14dd8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 19 Apr 2021 17:12:42 +0200 Subject: soc/intel/broadwell: Re-do SerialIO UART console support Use the same code from Lynx Point on Broadwell, and adjust as needed. Also add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P (Haswell ULT), UART 0 works. Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/37553 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/broadwell/pch/lpc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/broadwell/pch/lpc.c') diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index e32ae361762d..4b4aa9f36cf3 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -604,11 +604,12 @@ static unsigned long broadwell_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - if (CONFIG(INTEL_PCH_UART_CONSOLE)) + if (CONFIG(SERIALIO_UART_CONSOLE)) { current = acpi_write_dbg2_pci_uart(rsdp, current, - (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1) ? + (CONFIG_UART_FOR_CONSOLE == 1) ? PCH_DEV_UART1 : PCH_DEV_UART0, - ACPI_ACCESS_SIZE_BYTE_ACCESS); + ACPI_ACCESS_SIZE_DWORD_ACCESS); + } return acpi_write_hpet(device, current, rsdp); } -- cgit v1.2.3