From dbe7f893c0e3fffc4e9862d872d65df752feaf9d Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Fri, 14 Jul 2017 11:09:10 -0700
Subject: soc/intel/cannonlake: Call into FSP siliconinit

The following changes can make system call into FSP siliconinit and exit
from that until payloads.

1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.

Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/cannonlake/chip.c | 59 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 src/soc/intel/cannonlake/chip.c

(limited to 'src/soc/intel/cannonlake/chip.c')

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
new file mode 100644
index 000000000000..2f893e3d4896
--- /dev/null
+++ b/src/soc/intel/cannonlake/chip.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <chip.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <romstage_handoff.h>
+#include <soc/ramstage.h>
+#include <string.h>
+
+void soc_init_pre_device(void *chip_info)
+{
+	/* Perform silicon specific init. */
+	fsp_silicon_init(romstage_handoff_is_resume());
+}
+
+struct chip_operations soc_intel_cannonlake_ops = {
+	CHIP_NAME("Intel Cannonlake")
+	.init		= &soc_init_pre_device,
+};
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+	int i;
+	FSP_S_CONFIG *params = &supd->FspsConfig;
+
+	/* Set USB OC pin to 0 first */
+	for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
+		params->Usb2OverCurrentPin[i] = 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
+		params->Usb3OverCurrentPin[i] = 0;
+	}
+
+	mainboard_silicon_init_params(params);
+}
+
+/* Mainboard GPIO Configuration */
+__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
-- 
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