From d9c5b14f1efe82a902a7a4ed543015948364f296 Mon Sep 17 00:00:00 2001 From: MAULIK V VAGHELA Date: Mon, 14 Feb 2022 22:04:03 +0530 Subject: intelblocks/pcie: Correct mapping between LCAP port and coreboot index coreboot uses port index which is 0 based for all PCIe root ports. In case of PCIe remapping logic, coreboot reads LCAP register from PCIe configuration space which contains port number (mostly 1 based). This assumption might not be true for all the ports in coreboot. TBT's LCAP registers are returning port index which are based on 2. coreboot's PCIe remapping logic returns port index based on index 1. This patch adds variable to pcie_rp_config to pass lcap_port_base to the pcie remapping function, so coreboot can map any n-based LCAP encoding to 0-based indexing scheme. This patch updates correct lcap_port_base variable for all PCIe root ports for all SOCs, so that function returns correct 0-based index from LCAP port number. BUG=b:210933428 BRANCH=None TEST=Check if code compiles for all ADL boards Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f Signed-off-by: MAULIK V VAGHELA Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936 Reviewed-by: Subrata Banik Reviewed-by: Tim Wawrzynczak Reviewed-by: EricR Lai Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/jasperlake/chip.c') diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index a8e3c8812822..7f325c4f59b1 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -17,7 +17,7 @@ #include static const struct pcie_rp_group pch_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, { 0 } }; -- cgit v1.2.3