From 5bf42c6c23b462d9292e6854d3f334cf17e42825 Mon Sep 17 00:00:00 2001
From: Barnali Sarkar <barnali.sarkar@intel.com>
Date: Wed, 24 Aug 2016 20:48:46 +0530
Subject: soc/intel/skylake: Add FSP 2.0 support in romstage

Populate SoC related Memory initialization params.

Post memory init, set DISB, setup stack and MTRRs using the postcar
funtions provided in postcar_loader.c.

TEST=Build and boot kunimitsu, dram initialization done.
ramstage is loaded.

Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16315
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/skylake/reset.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc/intel/skylake/reset.c')

diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index ab251ce05f03..638a151a9d12 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -17,7 +17,7 @@
 #include <fsp/util.h>
 #include <reset.h>
 
-void chipset_handle_reset(enum fsp_status status)
+void chipset_handle_reset(uint32_t status)
 {
 	switch(status) {
 	case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
-- 
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