From d5bd8d54a32143c7d126a406eec1c3bcbf0240f5 Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Wed, 14 Dec 2022 11:37:55 +0000 Subject: soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handling After calling FSP MemoryInit API, if there is an error, some FSPs (such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB. Check existence of such a HOB and handle it accordingly. Change-Id: Icb5c31daa223ba6b06ba1b2de4f8808e0b27899e Signed-off-by: Tim Chu Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/72505 Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan --- src/soc/intel/xeon_sp/include/soc/romstage.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/xeon_sp/include') diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index a2adfed918f9..2fd8128918eb 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -10,5 +10,6 @@ void mainboard_memory_init_params(FSPM_UPD * mupd); void mainboard_rtc_failed(void); void save_dimm_info(void); void mainboard_ewl_check(void); +void mainboard_fsp_error_handle(void); #endif /* _SOC_ROMSTAGE_H_ */ -- cgit v1.2.3