From 117770d32468e63df37aee1c041b5dc7cc1d56d2 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 21 Jul 2022 15:40:03 -0700 Subject: soc/intel/alderlake: Enable Energy/Performance Bias control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to document 619503 ADL EDS Vol2, bit 18 of MSR_POWER_CTL must be set to be able to set the Energy/Performance Bias using MSR IA32_ENERGY_PERF_BIAS. Note that since this bit was not set until this patch, the `set_energy_perf_bias(ENERGY_POLICY_NORMAL);' call in `soc_core_init()` was systematically failing. BRANCH=firmware-brya-14505.B BUG=b:239853069 TEST=verify that EPB is set by coreboot Signed-off-by: Jeremy Compostella Change-Id: Ic24abdd7f63f4707b8996da4755a26be148efe4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66058 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index c2564ac4fa49..7308185be7b8 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -76,10 +76,11 @@ static void configure_misc(void) msr.hi = 0; wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); - /* Enable PROCHOT */ + /* Enable PROCHOT and Energy/Performance Bias control */ msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ + msr.lo |= (1 << 18); /* Energy/Performance Bias control */ wrmsr(MSR_POWER_CTL, msr); } -- cgit v1.2.3