From 9159e1c5278129ae71c12a2b9d3e274a82dd09cf Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 2 Jun 2022 16:49:48 -0700 Subject: soc/intel/alderlake: Support Raptor Lake VR Fast VMODE RaptorLake introduces the support of the Voltage Regulator Fast Vmode feature. When enabled, it makes the SoC throttle when the current exceeds the I_TRIP threshold. This threshold should be between Iccmax.app and Iccmax and take into account the specification of the Voltage Regulator of the system. This change provides a mean to: 1. Enable the feature via the `vr_config->enable_fast_vmode'. If no I_TRIP value is supplied FSPs picks an adapted I_TRIP value for the current SoC assuming a Voltage Regulator error accuracy of 6.5%. 2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip' field. These new fields are considered independent from the other `vr_config' fields so that the board configuration does not have to unnecessarily supply other VR settings to enable Fast VMode. Information about the Fast VMode Feature can be found in the following Intel documents: - 627270 ADL and RPL Processor Family Core and Uncore BIOS Specification - 724220 RaptorLake Platform Fast V-Mode - 686872 RaptorLake Lake U P H Platform BUG=b:243120082 BRANCH=firmware-brya-14505.B TEST=Read I_TRIP from the Pcode and verify consistency with a few `enable_fast_vmode' and `fast_vmode_i_trip' settings. Signed-off-by: Jeremy Compostella Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik Reviewed-by: Angel Pons --- src/soc/intel/alderlake/include/soc/vr_config.h | 19 +++++++++++++++++++ src/soc/intel/alderlake/vr_config.c | 12 ++++++++++++ 2 files changed, 31 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/alderlake/include/soc/vr_config.h b/src/soc/intel/alderlake/include/soc/vr_config.h index 316abc0dd2aa..41c2f6b55efc 100644 --- a/src/soc/intel/alderlake/include/soc/vr_config.h +++ b/src/soc/intel/alderlake/include/soc/vr_config.h @@ -8,6 +8,25 @@ #include struct vr_config { +#if CONFIG(SOC_INTEL_RAPTORLAKE) + /* + * When enabled, this feature makes the SoC throttle when the power + * consumption exceeds the I_TRIP threshold. + * + * FSPs sets a by default I_TRIP threshold adapted to the current SoC + * and assuming a Voltage Regulator error accuracy of 6.5%. + */ + bool enable_fast_vmode; + + /* + * VR Fast Vmode I_TRIP threshold. + * 0-255A in 1/4 A units. Example: 400 = 100A + + * This setting overrides the default value set by FSPs when Fast VMode + * is enabled. + */ + uint16_t fast_vmode_i_trip; +#endif /* The below settings will take effect when this is set to 1 for that domain. */ bool vr_config_enable; diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 159f4514bd07..4d649fbfeca5 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -254,6 +254,16 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 30) }, }; +static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg, + int domain, const struct vr_config *chip_cfg) +{ +#if CONFIG(SOC_INTEL_RAPTORLAKE) + s_cfg->EnableFastVmode[domain] = chip_cfg->enable_fast_vmode; + if (s_cfg->EnableFastVmode[domain]) + s_cfg->IccLimit[domain] = chip_cfg->fast_vmode_i_trip; +#endif +} + void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, int domain, const struct vr_config *chip_cfg) { @@ -299,6 +309,8 @@ void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, domain, mch_id, tdp); } + fill_vr_fast_vmode(s_cfg, domain, chip_cfg); + /* Check TdcTimeWindow and TdcCurrentLimit, Set TdcEnable and Set VR TDC Input current to root mean square */ if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) { -- cgit v1.2.3