From b739d80197d7a92ad357d0e45ea0f22b4a06b09f Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Fri, 29 Jul 2022 12:07:15 -0600 Subject: soc/intel/alderlake: Add IRQ constraints for CPU PCIe ports Copy the constraint from ADL-S to ADL-P. Fixes the following warning in Linux on System76 oryp9, which has an NVIDIA GPU on the bridge. pcieport 0000:00:01.0: can't derive routing for PCI INT A This, in turn, resolves an IRQ conflict with the PCH HDA device that would cause a stack track on every boot. irq 10: nobody cared (try booting with the "irqpoll" option) [<00000000bf549647>] azx_interrupt [snd_hda_codec] Disabling IRQ #10 Change-Id: I550c80105ff861d051170ed748149aeb25a545db Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/66285 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/fsp_params.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index ec4281d4b596..592afb8d974b 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -60,6 +60,12 @@ enum fsp_end_of_post { }; static const struct slot_irq_constraints irq_constraints[] = { + { + .slot = SA_DEV_SLOT_CPU_1, + .fns = { + FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_0, PCI_INT_A, PIRQ_A), + }, + }, { .slot = SA_DEV_SLOT_IGD, .fns = { -- cgit v1.2.3