From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8173/ddp.c | 20 +- src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 226 ++++++++++----------- src/soc/mediatek/mt8173/dramc_pi_calibration_api.c | 196 +++++++++--------- src/soc/mediatek/mt8173/dsi.c | 40 ++-- src/soc/mediatek/mt8173/emi.c | 8 +- src/soc/mediatek/mt8173/gpio_init.c | 4 +- src/soc/mediatek/mt8173/pll.c | 54 ++--- src/soc/mediatek/mt8173/pmic_wrap.c | 4 +- src/soc/mediatek/mt8173/spi.c | 8 +- 9 files changed, 280 insertions(+), 280 deletions(-) (limited to 'src/soc/mediatek/mt8173') diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 9f201fd0d4aa..555bfe905f63 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -60,17 +60,17 @@ static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk) static void disp_clock_on(void) { - clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON | - CG_CON0_SMI_LARB0 | - CG_CON0_MUTEX_32K | - CG_CON0_DISP_OVL0 | - CG_CON0_DISP_RDMA0 | - CG_CON0_DISP_COLOR0 | - CG_CON0_DISP_UFOE | - CG_CON0_DISP_OD); + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON | + CG_CON0_SMI_LARB0 | + CG_CON0_MUTEX_32K | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_UFOE | + CG_CON0_DISP_OD); - clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE | - CG_CON1_DSI0_DIGITAL); + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE | + CG_CON1_DSI0_DIGITAL); } void mtk_ddp_init(void) diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index f9bd5073ca28..58dce72e9431 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -74,17 +74,17 @@ static void mem_pll_pre_init(u32 channel) write32(&ch[channel].ddrphy_regs->mempll05_divider, 0x1 << 27); /* enable chip top memory clock */ - setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 4); + setbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 4); /* disable C/A and DQ M_CK clock gating */ - clrbits_le32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | - 0x1 << 1); + clrbits32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | + 0x1 << 1); /* enable spm control clock */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 15 | - 0x1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 15 | + 0x1 << 0); /* enable dramc 2X mode */ - setbits_le32(&ch[channel].ao_regs->ddr2ctl, 1 << 0); + setbits32(&ch[channel].ao_regs->ddr2ctl, 1 << 0); /* select internal clock path */ write32(&ch[channel].ddrphy_regs->peri[0], 0x21 << 24 | 0x27 << 16 | @@ -94,12 +94,12 @@ static void mem_pll_pre_init(u32 channel) 0x6 << 8 | 0x1e << 0); /* trigger to make memory clock correct phase */ - setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 | - 0x1 << 7); + setbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 | + 0x1 << 7); if (channel == CHANNEL_A) { /* select memory clock sync for channel A (internal source) */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3); + clrbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3); } } @@ -156,11 +156,11 @@ static void mem_pll_init_phase_sync(u32 channel) BIT(7) | BIT(5) | BIT(4) | BIT(0)); /* spm control clock enable */ - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll_divider, BIT(0), - BIT(1)); + clrsetbits32(&ch[channel].ddrphy_regs->mempll_divider, BIT(0), + BIT(1)); - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll_divider, BIT(1), - BIT(0)); + clrsetbits32(&ch[channel].ddrphy_regs->mempll_divider, BIT(1), + BIT(0)); } static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs) @@ -169,25 +169,25 @@ static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs) case MEMPLL_INIT: /* initial phase: zero out RG_MEPLL(2,3,4)_(REF_DL,FB)_DL */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs], - 0x1f << MEMPLL_REF_DL_SHIFT | - 0x1f << MEMPLL_FB_DL_SHIFT); + clrbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], + 0x1f << MEMPLL_REF_DL_SHIFT | + 0x1f << MEMPLL_FB_DL_SHIFT); break; case MEMPLL_REF_LAG: /* REF lag FBK, delay FBK */ - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs], - 0x1f << MEMPLL_REF_DL_SHIFT | - 0x1f << MEMPLL_FB_DL_SHIFT, - mempll->delay << MEMPLL_FB_DL_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], + 0x1f << MEMPLL_REF_DL_SHIFT | + 0x1f << MEMPLL_FB_DL_SHIFT, + mempll->delay << MEMPLL_FB_DL_SHIFT); break; case MEMPLL_REF_LEAD: /* REF lead FBK, delay REF */ - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs], - 0x1f << MEMPLL_REF_DL_SHIFT | - 0x1f << MEMPLL_FB_DL_SHIFT, - mempll->delay << MEMPLL_REF_DL_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], + 0x1f << MEMPLL_REF_DL_SHIFT | + 0x1f << MEMPLL_FB_DL_SHIFT, + mempll->delay << MEMPLL_REF_DL_SHIFT); }; } @@ -250,9 +250,9 @@ static void mem_pll_phase_cali(u32 channel) /* 1. set jitter meter count number to 1024 for mempll 2 3 4 */ for (i = 0; i < 3; i++) - clrsetbits_le32(&ch[channel].ddrphy_regs->jmeter[i], - JMETER_COUNTER_MASK, - JMETER_COUNT << JMETER_COUNTER_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->jmeter[i], + JMETER_COUNTER_MASK, + JMETER_COUNT << JMETER_COUNTER_SHIFT); while (1) { @@ -266,8 +266,8 @@ static void mem_pll_phase_cali(u32 channel) /* 2. enable mempll 2 3 4 jitter meter */ for (i = 0; i < 3; i++) - setbits_le32(&ch[channel].ddrphy_regs->jmeter[i], - JMETER_EN_BIT); + setbits32(&ch[channel].ddrphy_regs->jmeter[i], + JMETER_EN_BIT); /* 3. wait for jitter meter complete */ udelay(JMETER_WAIT_DONE_US); @@ -281,8 +281,8 @@ static void mem_pll_phase_cali(u32 channel) /* 5. disable mempll 2 3 4 jitter meter */ for (i = 0; i < 3; i++) - clrbits_le32(&ch[channel].ddrphy_regs->jmeter[i], - JMETER_EN_BIT); + clrbits32(&ch[channel].ddrphy_regs->jmeter[i], + JMETER_EN_BIT); /* 6. all done early break */ if (mempll[0].done && mempll[1].done && mempll[2].done) @@ -336,58 +336,58 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params) udelay(2); /* mempll2_en -> mempll4_en -> mempll3_en */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); udelay(100); /* mempll_bias_lpf_en */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[3], 1 << 7); + setbits32(&ch[channel].ddrphy_regs->mempll[3], 1 << 7); udelay(30); /* select mempll4 band register */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); + setbits32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); + clrbits32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); /* PLL ready */ /* disable mempll2_en -> mempll4_en -> mempll3_en */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); /* disable autok mempll2_en -> mempll4_en -> mempll3_en */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 23); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 23); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 23); + clrbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 23); + clrbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 23); + clrbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 23); udelay(1); /* mempll[2->4->3]_fb_mck_sel=1 (switch to outer loop) */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[6], 1 << 25); - setbits_le32(&ch[channel].ddrphy_regs->mempll[12], 1 << 25); - setbits_le32(&ch[channel].ddrphy_regs->mempll[9], 1 << 25); + setbits32(&ch[channel].ddrphy_regs->mempll[6], 1 << 25); + setbits32(&ch[channel].ddrphy_regs->mempll[12], 1 << 25); + setbits32(&ch[channel].ddrphy_regs->mempll[9], 1 << 25); udelay(1); /* enable mempll2_en -> mempll4_en -> mempll3_en */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); } /* mempll new power-on */ write32(&mtk_spm->poweron_config_set, 0x1 << 0 | SPM_PROJECT_CODE << 16); /* request mempll reset/pdn mode */ - setbits_le32(&mtk_spm->power_on_val0, 0x1 << 27); + setbits32(&mtk_spm->power_on_val0, 0x1 << 27); udelay(2); /* unrequest mempll reset/pdn mode and wait settle */ - clrbits_le32(&mtk_spm->power_on_val0, 0x1 << 27); + clrbits32(&mtk_spm->power_on_val0, 0x1 << 27); udelay(31); /* PLL ready */ @@ -628,16 +628,16 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) write32(&ch[channel].ao_regs->padctl7, 0x0); /* CLKTDN, DS0TDN, DS1TDN, DS2TDN, DS3TDN */ - setbits_le32(&ch[channel].ddrphy_regs->tdsel[2], 0x1 << 31 | + setbits32(&ch[channel].ddrphy_regs->tdsel[2], 0x1 << 31 | 0x1 << 29 | 0x1 << 27 | 0x1 << 25 | 0x1 << 1); /* DISABLE_PERBANK_REFRESH */ - clrbits_le32(&ch[channel].ao_regs->rkcfg, 0x1 << 7); + clrbits32(&ch[channel].ao_regs->rkcfg, 0x1 << 7); /* clear R_DMREFTHD to reduce MR4 wait refresh queue time */ - clrbits_le32(&ch[channel].ao_regs->conf2, 0x7 << 24); + clrbits32(&ch[channel].ao_regs->conf2, 0x7 << 24); /* duty default value */ write32(&ch[channel].ddrphy_regs->phyclkduty, 0x1 << 28 | @@ -645,7 +645,7 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) if (!dual_rank_set) { /* single rank, CKE1 always off */ - setbits_le32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 21); + setbits32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 21); } /* default dqs rx perbit input delay */ @@ -662,72 +662,72 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) void div2_phase_sync(void) { - clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, + clrbits32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, 1 << MEMCLKENB_SHIFT); udelay(1); - setbits_le32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, + setbits32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, 1 << MEMCLKENB_SHIFT); } void dramc_phy_reset(u32 channel) { /* reset phy */ - setbits_le32(&ch[channel].ddrphy_regs->phyctl1, + setbits32(&ch[channel].ddrphy_regs->phyctl1, 1 << PHYCTL1_PHYRST_SHIFT); /* read data counter reset */ - setbits_le32(&ch[channel].ao_regs->gddr3ctl1, + setbits32(&ch[channel].ao_regs->gddr3ctl1, 1 << GDDR3CTL1_RDATRST_SHIFT); udelay(1); /* delay 1ns */ - clrbits_le32(&ch[channel].ao_regs->gddr3ctl1, + clrbits32(&ch[channel].ao_regs->gddr3ctl1, 1 << GDDR3CTL1_RDATRST_SHIFT); - clrbits_le32(&ch[channel].ddrphy_regs->phyctl1, + clrbits32(&ch[channel].ddrphy_regs->phyctl1, 1 << PHYCTL1_PHYRST_SHIFT); } void dramc_runtime_config(u32 channel, const struct mt8173_sdram_params *sdram_params) { - setbits_le32(&ch[channel].ddrphy_regs->dqsgctl, + setbits32(&ch[channel].ddrphy_regs->dqsgctl, BIT(17)|BIT(18)); /* enable hw gating */ - setbits_le32(&ch[channel].ao_regs->dqscal0, - 1 << DQSCAL0_STBCALEN_SHIFT); + setbits32(&ch[channel].ao_regs->dqscal0, + 1 << DQSCAL0_STBCALEN_SHIFT); /* if frequency >1600, tCKE should >7 clk */ - setbits_le32(&ch[channel].ao_regs->dummy, 0x1 << 4); + setbits32(&ch[channel].ao_regs->dummy, 0x1 << 4); if (sdram_params->dram_freq * 2 < 1600 * MHz) die("set tCKE error in runtime config"); /* DDRPHY C/A and DQ M_CK clock gating enable */ - setbits_le32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | + setbits32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | 0x1 << 1); - setbits_le32(&ch[channel].ao_regs->perfctl0, BIT(19) | BIT(14) | + setbits32(&ch[channel].ao_regs->perfctl0, BIT(19) | BIT(14) | BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(4) | BIT(0)); /* ZQCS_ENABLE */ if (sdram_params->emi_set.cona & 0x1) { /* dual channel, clear ZQCSCNT */ - clrbits_le32(&ch[channel].ao_regs->spcmd, 0xff << 16); + clrbits32(&ch[channel].ao_regs->spcmd, 0xff << 16); /* set ZQCSMASK for different channels */ if (channel == CHANNEL_A) { - clrbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); + clrbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); } else { - setbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); + setbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); } /* enable ZQCSDUAL */ - setbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 25); + setbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 25); } else { /* single channel, set ZQCSCNT */ - setbits_le32(&ch[channel].ao_regs->spcmd, 0x8 << 16); + setbits32(&ch[channel].ao_regs->spcmd, 0x8 << 16); } } @@ -736,17 +736,17 @@ void transfer_to_spm_control(void) u32 msk; msk = BIT(7) | BIT(11) | BIT(15); - clrbits_le32(&mtk_apmixed->ap_pll_con3, msk); + clrbits32(&mtk_apmixed->ap_pll_con3, msk); msk = BIT(0) | BIT(4) | BIT(8); - clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk); + clrbits32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk); msk = BIT(0) | BIT(8); - clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[3], msk); + clrbits32(&ch[CHANNEL_B].ddrphy_regs->peri[3], msk); msk = BIT(0) | BIT(9) | BIT(10) | BIT(11) | BIT(16) | BIT(24); - clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[2], msk); - clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[2], msk); + clrbits32(&ch[CHANNEL_A].ddrphy_regs->peri[2], msk); + clrbits32(&ch[CHANNEL_B].ddrphy_regs->peri[2], msk); } void transfer_to_reg_control(void) @@ -754,17 +754,17 @@ void transfer_to_reg_control(void) u32 val; val = BIT(7) | BIT(11) | BIT(15); - setbits_le32(&mtk_apmixed->ap_pll_con3, val); + setbits32(&mtk_apmixed->ap_pll_con3, val); val = BIT(0) | BIT(4) | BIT(8); - setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val); + setbits32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val); val = BIT(0) | BIT(8); write32(&ch[CHANNEL_B].ddrphy_regs->peri[3], val); val = BIT(0) | BIT(9) | BIT(10) | BIT(11) | BIT(16) | BIT(24); - setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[2], val); - setbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[2], val); + setbits32(&ch[CHANNEL_A].ddrphy_regs->peri[2], val); + setbits32(&ch[CHANNEL_B].ddrphy_regs->peri[2], val); } u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, @@ -776,9 +776,9 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, die("Invalid loopcount of engine2!"); /* Disable Test Agent1, Test Agent2 write/read */ - clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST1_EN | - CONF2_TEST2R_EN | - CONF2_TEST2W_EN); + clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST1_EN | + CONF2_TEST2R_EN | + CONF2_TEST2W_EN); /* 1. set pattern, base address, offset address */ write32(&ch[channel].nao_regs->test2_1, test2_1); @@ -794,49 +794,49 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, switch (testaudpat) { case XTALK: /* TESTAUDPAT = 0 */ - clrbits_le32(&ch[channel].ao_regs->test2_3, - TEST2_3_TESTAUDPAT_EN); + clrbits32(&ch[channel].ao_regs->test2_3, + TEST2_3_TESTAUDPAT_EN); /* TESTXTALKPAT = 1, select xtalk pattern * TESTAUDMODE = 0, read only * TESTAUDBITINV = 0, no bit inversion */ - clrsetbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTAUDBITINV_EN | - TEST2_4_TESTAUDMODE_EN, - TEST2_4_TESTXTALKPAT_EN); + clrsetbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTAUDBITINV_EN | + TEST2_4_TESTAUDMODE_EN, + TEST2_4_TESTXTALKPAT_EN); break; case AUDIO: /* TESTAUDPAT = 1 */ - setbits_le32(&ch[channel].ao_regs->test2_3, - TEST2_3_TESTAUDPAT_EN); + setbits32(&ch[channel].ao_regs->test2_3, + TEST2_3_TESTAUDPAT_EN); /* TESTXTALKPAT = 0 * TESTAUDINIT = 0x11 * TESTAUDINC = 0x0d * TESTAUDBITINV = 1 * TESTAUDMODE = 1 */ - clrsetbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTXTALKPAT_EN | - TEST2_4_TESTAUDINIT_MASK | - TEST2_4_TESTAUDINC_MASK, - TEST2_4_TESTAUDMODE_EN | - TEST2_4_TESTAUDBITINV_EN | - 0x11 << TEST2_4_TESTAUDINIT_SHIFT | - 0xd << TEST2_4_TESTAUDINC_SHIFT); + clrsetbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTXTALKPAT_EN | + TEST2_4_TESTAUDINIT_MASK | + TEST2_4_TESTAUDINC_MASK, + TEST2_4_TESTAUDMODE_EN | + TEST2_4_TESTAUDBITINV_EN | + 0x11 << TEST2_4_TESTAUDINIT_SHIFT | + 0xd << TEST2_4_TESTAUDINC_SHIFT); break; case ISI: /* TESTAUDPAT = 0 */ - clrbits_le32(&ch[channel].ao_regs->test2_3, - TEST2_3_TESTAUDPAT_EN); + clrbits32(&ch[channel].ao_regs->test2_3, + TEST2_3_TESTAUDPAT_EN); /* TESTXTALKPAT = 0 */ - clrbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTXTALKPAT_EN); + clrbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTXTALKPAT_EN); } /* 3. set loop number */ - clrsetbits_le32(&ch[channel].ao_regs->test2_3, TEST2_3_TESTCNT_MASK, - log2loopcount << TEST2_3_TESTCNT_SHIFT); + clrsetbits32(&ch[channel].ao_regs->test2_3, TEST2_3_TESTCNT_MASK, + log2loopcount << TEST2_3_TESTCNT_SHIFT); /* 4. enable read/write test */ if (wr == TE_OP_READ_CHECK) { @@ -844,15 +844,15 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, /* if audio pattern, enable read only */ /* (disable write after read), */ /* AUDMODE=0x48[15]=0 */ - clrbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTAUDMODE_EN); + clrbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTAUDMODE_EN); } /* enable read, 0x008[30:30] */ - setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); + setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); } else if (wr == TE_OP_WRITE_READ_CHECK) { /* enable write, 0x008[31:31] */ - setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); + setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); /* check "read data compare ready" bit */ do { @@ -860,8 +860,8 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, } while ((value & (1 << TESTRPT_DM_CMP_CPT_SHIFT)) == 0); /* Disable Test Agent2 write and enable Test Agent2 read */ - clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); - setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); + clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); + setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); } /* 5 check "read data compare ready" bit */ @@ -876,7 +876,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, value = read32(&ch[channel].nao_regs->cmp_err); /* 6 disable read */ - clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); + clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); /* return CMP_ERR result, pass: 0, failure: otherwise */ return value; diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 0a8e69be1e9b..a22d7e22d199 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -42,14 +42,14 @@ void sw_impedance_cal(u32 channel, params->impedance_drvp << 12 | params->impedance_drvn << 8; /* DQS and DQ */ - clrsetbits_le32(&ch[channel].ao_regs->iodrv6, mask, value); + clrsetbits32(&ch[channel].ao_regs->iodrv6, mask, value); /* CLK and CMD */ - clrsetbits_le32(&ch[channel].ao_regs->drvctl1, mask, value); - clrsetbits_le32(&ch[channel].ddrphy_regs->drvctl1, mask, value); + clrsetbits32(&ch[channel].ao_regs->drvctl1, mask, value); + clrsetbits32(&ch[channel].ddrphy_regs->drvctl1, mask, value); /* DQ_2 and CMD_2 */ - clrsetbits_le32(&ch[channel].ao_regs->iodrv4, mask, value); + clrsetbits32(&ch[channel].ao_regs->iodrv4, mask, value); /* disable impcal calibration */ - clrbits_le32(&ch[channel].ao_regs->impcal, 1 << IMP_CALI_ENP_SHIFT | + clrbits32(&ch[channel].ao_regs->impcal, 1 << IMP_CALI_ENP_SHIFT | 1 << IMP_CALI_ENN_SHIFT | 1 << IMP_CALI_EN_SHIFT | 0xf << IMP_CALI_DRVP_SHIFT | @@ -89,40 +89,40 @@ void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params) /* set CA pins output delay */ for (i = 0; i < (CATRAINING_NUM - 1); i++) { order = ca_order[channel][i]; - clrsetbits_le32(&ch[channel].ddrphy_regs->cmddly[cmd_order[i]], - 0xf << shift[i], ca_shift[order] << shift[i]); + clrsetbits32(&ch[channel].ddrphy_regs->cmddly[cmd_order[i]], + 0xf << shift[i], ca_shift[order] << shift[i]); } order = ca_order[channel][9]; - clrsetbits_le32(&ch[channel].ddrphy_regs->dqscal0, - 0xf << DQSCAL0_RA14_SHIFT, - ca_shift[order] << DQSCAL0_RA14_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->dqscal0, + 0xf << DQSCAL0_RA14_SHIFT, + ca_shift[order] << DQSCAL0_RA14_SHIFT); /* CKE and CS delay */ ca_shift_avg32 = (u32)(ca_shift_avg8 + (CATRAINING_NUM >> 1)); ca_shift_avg32 /= (u32)CATRAINING_NUM; /* CKEDLY */ - clrsetbits_le32(&ch[channel].ddrphy_regs->cmddly[4], - 0x1f << CMDDLY4_CS_SHIFT | - 0x1f << CMDDLY4_CKE_SHIFT, - ca_shift_avg32 << CMDDLY4_CS_SHIFT | - ca_shift_avg32 << CMDDLY4_CKE_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->cmddly[4], + 0x1f << CMDDLY4_CS_SHIFT | + 0x1f << CMDDLY4_CKE_SHIFT, + ca_shift_avg32 << CMDDLY4_CS_SHIFT | + ca_shift_avg32 << CMDDLY4_CKE_SHIFT); /* CKE1DLY */ - clrsetbits_le32(&ch[channel].ao_regs->dqscal1, - 0x1f << DQSCAL1_CKE1_SHIFT, - ca_shift_avg32 << DQSCAL1_CKE1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqscal1, + 0x1f << DQSCAL1_CKE1_SHIFT, + ca_shift_avg32 << DQSCAL1_CKE1_SHIFT); /* CS1DLY */ - clrsetbits_le32(&ch[channel].ddrphy_regs->padctl1, - 0xf << PADCTL1_CS1_SHIFT, - ca_shift_avg32 << PADCTL1_CS1_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->padctl1, + 0xf << PADCTL1_CS1_SHIFT, + ca_shift_avg32 << PADCTL1_CS1_SHIFT); /* set max center into clk output delay */ - clrsetbits_le32(&ch[channel].ddrphy_regs->padctl1, - 0xf << PADCTL1_CLK_SHIFT, - ca_max_center << PADCTL1_CLK_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->padctl1, + 0xf << PADCTL1_CLK_SHIFT, + ca_max_center << PADCTL1_CLK_SHIFT); dramc_dbg_msg("=========================================\n"); dramc_dbg_msg(" [Channel %d] CA training\n", channel); @@ -155,8 +155,8 @@ void write_leveling(u32 channel, const struct mt8173_sdram_params *sdram_params) write32(&ch[channel].ddrphy_regs->padctl3, value); /* DQM */ - clrsetbits_le32(&ch[channel].ddrphy_regs->padctl2, MASK_PADCTL2_32BIT, - (value << PADCTL2_SHIFT) & MASK_PADCTL2_32BIT); + clrsetbits32(&ch[channel].ddrphy_regs->padctl2, MASK_PADCTL2_32BIT, + (value << PADCTL2_SHIFT) & MASK_PADCTL2_32BIT); /* DQ */ for (byte_i = 0; byte_i < DQS_NUMBER; byte_i++) { @@ -203,10 +203,10 @@ static void set_gw_coarse_factor(u32 channel, u8 curr_val) curr_val_p1 = curr_val + 2; /* diff is 0.5T */ /* Rank 0 P0/P1 coarse tune settings */ - clrsetbits_le32(&ch[channel].ao_regs->dqsctl1, - 0xf << DQSCTL1_DQSINCTL_SHIFT, - coarse_tune_start << DQSCTL1_DQSINCTL_SHIFT & - 0xf << DQSCTL1_DQSINCTL_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqsctl1, + 0xf << DQSCTL1_DQSINCTL_SHIFT, + coarse_tune_start << DQSCTL1_DQSINCTL_SHIFT & + 0xf << DQSCTL1_DQSINCTL_SHIFT); /* DQSINCTL does not have P1. */ /* Need to use TXDLY_DQSGATE/TXDLY_DQSGATE_P1 to set */ @@ -214,33 +214,33 @@ static void set_gw_coarse_factor(u32 channel, u8 curr_val) selph2_dqsgate = (curr_val >> 2) - coarse_tune_start; selph2_dqsgate_p1 = (curr_val_p1 >> 2) - coarse_tune_start; - clrsetbits_le32(&ch[channel].ao_regs->selph2, - 0x7 << SELPH2_TXDLY_DQSGATE_SHIFT | - 0x7 << SELPH2_TXDLY_DQSGATE_P1_SHIFT, - selph2_dqsgate << SELPH2_TXDLY_DQSGATE_SHIFT | - selph2_dqsgate_p1 << SELPH2_TXDLY_DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph2, + 0x7 << SELPH2_TXDLY_DQSGATE_SHIFT | + 0x7 << SELPH2_TXDLY_DQSGATE_P1_SHIFT, + selph2_dqsgate << SELPH2_TXDLY_DQSGATE_SHIFT | + selph2_dqsgate_p1 << SELPH2_TXDLY_DQSGATE_P1_SHIFT); /* dly_DQSGATE and dly_DQSGATE_P1 */ - clrsetbits_le32(&ch[channel].ao_regs->selph5, - 0x3 << SELPH5_DLY_DQSGATE_SHIFT | - 0x3 << SELPH5_DLY_DQSGATE_P1_SHIFT, - (curr_val & 0x3) << SELPH5_DLY_DQSGATE_SHIFT | - (curr_val_p1 & 0x3) << SELPH5_DLY_DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph5, + 0x3 << SELPH5_DLY_DQSGATE_SHIFT | + 0x3 << SELPH5_DLY_DQSGATE_P1_SHIFT, + (curr_val & 0x3) << SELPH5_DLY_DQSGATE_SHIFT | + (curr_val_p1 & 0x3) << SELPH5_DLY_DQSGATE_P1_SHIFT); } static void set_gw_fine_factor(u32 channel, u8 curr_val, u8 rank) { u32 set = curr_val & (0x7f << DQSIEN_DQS0IEN_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->dqsien[rank], - 0x7f << DQSIEN_DQS0IEN_SHIFT | - 0x7f << DQSIEN_DQS1IEN_SHIFT | - 0x7f << DQSIEN_DQS2IEN_SHIFT | - 0x7f << DQSIEN_DQS3IEN_SHIFT, - set << DQSIEN_DQS0IEN_SHIFT | - set << DQSIEN_DQS1IEN_SHIFT | - set << DQSIEN_DQS2IEN_SHIFT | - set << DQSIEN_DQS3IEN_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqsien[rank], + 0x7f << DQSIEN_DQS0IEN_SHIFT | + 0x7f << DQSIEN_DQS1IEN_SHIFT | + 0x7f << DQSIEN_DQS2IEN_SHIFT | + 0x7f << DQSIEN_DQS3IEN_SHIFT, + set << DQSIEN_DQS0IEN_SHIFT | + set << DQSIEN_DQS1IEN_SHIFT | + set << DQSIEN_DQS2IEN_SHIFT | + set << DQSIEN_DQS3IEN_SHIFT); } static void set_gw_coarse_factor_rank1(u32 channel, u8 curr_val, u8 dqsinctl) @@ -249,33 +249,33 @@ static void set_gw_coarse_factor_rank1(u32 channel, u8 curr_val, u8 dqsinctl) curr_val_p1 = curr_val + 2; /* diff is 0.5T */ - clrsetbits_le32(&ch[channel].ao_regs->dqsctl2, - 0xf << DQSCTL2_DQSINCTL_SHIFT, - dqsinctl << DQSCTL2_DQSINCTL_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqsctl2, + 0xf << DQSCTL2_DQSINCTL_SHIFT, + dqsinctl << DQSCTL2_DQSINCTL_SHIFT); /* TXDLY_R1DQSGATE and TXDLY_R1DQSGATE_P1 */ r1dqsgate = (curr_val >> 2) - dqsinctl; r1dqsgate_p1 = (curr_val_p1 >> 2) - dqsinctl; - clrsetbits_le32(&ch[channel].ao_regs->selph6_1, - 0x7 << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | - 0x7 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT, - r1dqsgate << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | - r1dqsgate_p1 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph6_1, + 0x7 << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | + 0x7 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT, + r1dqsgate << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | + r1dqsgate_p1 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT); /* dly_R1DQSGATE and dly_R1DQSGATE_P1 */ - clrsetbits_le32(&ch[channel].ao_regs->selph6_1, - 0x3 << SELPH6_1_DLY_R1DQSGATE_SHIFT | - 0x3 << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT, - (curr_val & 0x3) << SELPH6_1_DLY_R1DQSGATE_SHIFT | - (curr_val_p1 & 0x3) << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph6_1, + 0x3 << SELPH6_1_DLY_R1DQSGATE_SHIFT | + 0x3 << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT, + (curr_val & 0x3) << SELPH6_1_DLY_R1DQSGATE_SHIFT | + (curr_val_p1 & 0x3) << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT); } static void dqs_gw_counter_reset(u32 channel) { /* reset dqs counter (1 to 0) */ - setbits_le32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); - clrbits_le32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + setbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + clrbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); dramc_phy_reset(channel); } @@ -357,15 +357,15 @@ void rx_dqs_gating_cal(u32 channel, u8 rank, u8 gw_coarse_val, gw_fine_val; /* disable HW gating */ - clrbits_le32(&ch[channel].ao_regs->dqscal0, + clrbits32(&ch[channel].ao_regs->dqscal0, 1 << DQSCAL0_STBCALEN_SHIFT); /* enable DQS gating window counter */ - setbits_le32(&ch[channel].ao_regs->dqsctl1, + setbits32(&ch[channel].ao_regs->dqsctl1, 1 << DQSCTL1_DQSIENMODE_SHIFT); - setbits_le32(&ch[channel].ao_regs->spcmd, + setbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTEN_SHIFT); /* dual-phase DQS clock gating control enabling */ - setbits_le32(&ch[channel].ddrphy_regs->dqsgctl, + setbits32(&ch[channel].ddrphy_regs->dqsgctl, 1 << DQSGCTL_DQSGDUALP_SHIFT); /* gating calibration value */ @@ -418,7 +418,7 @@ void dual_rank_rx_dqs_gating_cal(u32 channel, dqsinctl = (dqsinctl >> DQSCTL1_DQSINCTL_SHIFT) & (0xf << 0); /* swap cs0 and cs1 */ - setbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + setbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* rank 1 gw calibration */ rx_dqs_gating_cal(channel, 1, sdram_params); @@ -429,7 +429,7 @@ void dual_rank_rx_dqs_gating_cal(u32 channel, set_gw_fine_factor(channel, opt_gw_fine_value[channel][1], 1); /* swap cs back */ - clrbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* set rank 0 coarse tune and fine tune back */ set_gw_coarse_factor(channel, opt_gw_coarse_value[channel][0]); @@ -446,15 +446,15 @@ void dramc_rankinctl_config(u32 channel, value = min(opt_gw_coarse_value[channel][0], opt_gw_coarse_value[channel][1]) >> 2; - clrsetbits_le32(&ch[channel].ao_regs->dummy, 0xf, value); + clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value); /* RANKINCTL = RANKINCTL_ROOT1 */ - clrsetbits_le32(&ch[channel].ao_regs->dqscal1, - 0xf << 16, value << 16); + clrsetbits32(&ch[channel].ao_regs->dqscal1, + 0xf << 16, value << 16); } /* disable per-bank refresh when refresh rate >= 5 */ - setbits_le32(&ch[channel].ao_regs->rkcfg, - 1 << RKCFG_PBREF_DISBYRATE_SHIFT); + setbits32(&ch[channel].ao_regs->rkcfg, + 1 << RKCFG_PBREF_DISBYRATE_SHIFT); } u32 dram_k_perbit(u32 channel) @@ -624,11 +624,11 @@ void clk_duty_cal(u32 channel) max_duty_sel = max_duty = 1; - clrsetbits_le32(&ch[channel].ddrphy_regs->phyclkduty, - 0x3 << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT | - 1 << PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT, - 1 << PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT | - max_duty << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->phyclkduty, + 0x3 << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT | + 1 << PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT, + 1 << PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT | + max_duty << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT); max_win_size = read32(&ch[channel].ddrphy_regs->phyclkduty); @@ -639,26 +639,26 @@ void clk_duty_cal(u32 channel) static void set_dle_factor(u32 channel, u8 curr_val) { - clrsetbits_le32(&ch[channel].ao_regs->ddr2ctl, - 0x7 << DDR2CTL_DATLAT_SHIFT, - (curr_val & 0x7) << DDR2CTL_DATLAT_SHIFT); + clrsetbits32(&ch[channel].ao_regs->ddr2ctl, + 0x7 << DDR2CTL_DATLAT_SHIFT, + (curr_val & 0x7) << DDR2CTL_DATLAT_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->padctl4, - 0x1 << PADCTL4_DATLAT3_SHIFT, - ((curr_val >> 3) & 0x1) << PADCTL4_DATLAT3_SHIFT); + clrsetbits32(&ch[channel].ao_regs->padctl4, + 0x1 << PADCTL4_DATLAT3_SHIFT, + ((curr_val >> 3) & 0x1) << PADCTL4_DATLAT3_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->phyctl1, - 0x1 << PHYCTL1_DATLAT4_SHIFT, - ((curr_val >> 4) & 0x1) << PHYCTL1_DATLAT4_SHIFT); + clrsetbits32(&ch[channel].ao_regs->phyctl1, + 0x1 << PHYCTL1_DATLAT4_SHIFT, + ((curr_val >> 4) & 0x1) << PHYCTL1_DATLAT4_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->misc, - 0x1f << MISC_DATLAT_DSEL_SHIFT, - (curr_val - 8) << MISC_DATLAT_DSEL_SHIFT); + clrsetbits32(&ch[channel].ao_regs->misc, + 0x1f << MISC_DATLAT_DSEL_SHIFT, + (curr_val - 8) << MISC_DATLAT_DSEL_SHIFT); /* optimize bandwidth for HW run time test engine use */ - clrsetbits_le32(&ch[channel].ao_regs->misc, - 0x1f << MISC_LATNORMP_SHIFT, - (curr_val - 3) << MISC_LATNORMP_SHIFT); + clrsetbits32(&ch[channel].ao_regs->misc, + 0x1f << MISC_LATNORMP_SHIFT, + (curr_val - 3) << MISC_LATNORMP_SHIFT); } void dual_rank_rx_datlat_cal(u32 channel, @@ -670,7 +670,7 @@ void dual_rank_rx_datlat_cal(u32 channel, r0_dle_setting = rx_datlat_cal(channel, 0, sdram_params); /* swap cs0 and cs1 */ - setbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + setbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* set rank 1 coarse tune and fine tune back */ set_gw_coarse_factor(channel, opt_gw_coarse_value[channel][1]); @@ -684,7 +684,7 @@ void dual_rank_rx_datlat_cal(u32 channel, set_gw_fine_factor(channel, opt_gw_fine_value[channel][0], 0); /* swap cs back */ - clrbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* output dle setting of rank 0 and 1 */ dramc_dbg_msg("[DLE] Rank 0 DLE calibrated setting = %xh.\n" @@ -715,7 +715,7 @@ u8 rx_datlat_cal(u32 channel, u8 rank, channel, rank); dramc_dbg_msg("=========================================\n"); - clrbits_le32(&ch[channel].ao_regs->mckdly, + clrbits32(&ch[channel].ao_regs->mckdly, 0x11 << MCKDLY_DQIENQKEND_SHIFT | 0x1 << MCKDLY_DQIENLAT_SHIFT); diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index b6ff0bc51f9c..dae23f5a0c05 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -40,16 +40,16 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) write32(&mipi_tx0->dsi_bg_con, reg); udelay(30); - clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, - 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); + clrsetbits32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, + 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); - setbits_le32(&mipi_tx0->dsi_con, - RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); + setbits32(&mipi_tx0->dsi_con, + RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); - clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, - RG_DSI_MPPLL_SDM_PWR_ON); + clrsetbits32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, + RG_DSI_MPPLL_SDM_PWR_ON); - clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); if (data_rate > 500) { txdiv0 = 0; @@ -70,9 +70,9 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) txdiv1 = 2; } - clrsetbits_le32(&mipi_tx0->dsi_pll_con0, - RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | - RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); + clrsetbits32(&mipi_tx0->dsi_pll_con0, + RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | + RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); /** * PLL PCW config @@ -86,25 +86,25 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) pcw /= 13; write32(&mipi_tx0->dsi_pll_con2, pcw); - setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); + setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); - setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); + setbits32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); for (i = 0; i < lanes; i++) - setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); + setbits32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); - setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + setbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); udelay(40); - clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); - clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); + clrbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); + clrbits32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); } void mtk_dsi_reset(void) { - setbits_le32(&dsi0->dsi_con_ctrl, 3); - clrbits_le32(&dsi0->dsi_con_ctrl, 1); + setbits32(&dsi0->dsi_con_ctrl, 3); + clrbits32(&dsi0->dsi_con_ctrl, 1); } void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) @@ -131,7 +131,7 @@ void mtk_dsi_pin_drv_ctrl(void) struct stopwatch sw; uint32_t pwr_ack; - setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON); + setbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON); stopwatch_init_usecs_expire(&sw, 1000); @@ -143,5 +143,5 @@ void mtk_dsi_pin_drv_ctrl(void) pwr_ack = read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK; } while (pwr_ack == 0); - clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); + clrbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); } diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index be84668abee5..f3ea7614e451 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -166,11 +166,11 @@ size_t sdram_size(void) static void init_4GB_mode(void) { if (sdram_size() == (size_t)4 * GiB) { - setbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); - setbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); + setbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); + setbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); } else { - clrbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); - clrbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); + clrbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); + clrbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); } } diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index e991a5f75dff..c701034a52ec 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -25,14 +25,14 @@ */ static void set_gpi_from_mipi(void) { - setbits_le32(&mt8173_mipi->mipi_rx_ana4c, + setbits32(&mt8173_mipi->mipi_rx_ana4c, 1 << 0 | /* RG_MIPI_GPI0_IES GPI47 */ 1 << 6 | /* RG_MIPI_GPI1_IES GPI48 */ 1 << 12 | /* RG_MIPI_GPI2_IES GPI49 */ 1 << 18 | /* RG_MIPI_GPI3_IES GPI50 */ 1 << 24); /* RF_MIPI_GPI4_IES GPI51 */ - setbits_le32(&mt8173_mipi->mipi_rx_ana50, + setbits32(&mt8173_mipi->mipi_rx_ana50, 1 << 0 | /* RG_MIPI_GPI5_IES GPI52 */ 1 << 6 | /* RG_MIPI_GPI6_IES GPI53 */ 1 << 12 | /* RG_MIPI_GPI7_IES GPI54 */ diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index e1c1bff6d537..494fcadbacaf 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -296,7 +296,7 @@ static const struct rate rates[] = { void pll_set_pcw_change(const struct pll *pll) { - setbits_le32(pll->pcw_reg, PLL_PCW_CHG); + setbits32(pll->pcw_reg, PLL_PCW_CHG); } void mt_pll_init(void) @@ -313,7 +313,7 @@ void mt_pll_init(void) * xPLL PWR ON **************/ for (i = 0; i < APMIXED_NR_PLL; i++) - setbits_le32(plls[i].pwr_reg, PLL_PWR_ON); + setbits32(plls[i].pwr_reg, PLL_PWR_ON); /* wait for xPLL_PWR_ON ready (min delay is 1us) */ udelay(PLL_PWR_ON_DELAY); @@ -322,7 +322,7 @@ void mt_pll_init(void) * xPLL ISO Disable *******************/ for (i = 0; i < APMIXED_NR_PLL; i++) - clrbits_le32(plls[i].pwr_reg, PLL_ISO); + clrbits32(plls[i].pwr_reg, PLL_ISO); /******************** * xPLL Frequency Set @@ -334,7 +334,7 @@ void mt_pll_init(void) * xPLL Frequency Enable ************************/ for (i = 0; i < APMIXED_NR_PLL; i++) - setbits_le32(plls[i].reg, PLL_EN); + setbits32(plls[i].reg, PLL_EN); udelay(PLL_EN_DELAY); /* wait for PLL stable (min delay is 20us) */ @@ -343,7 +343,7 @@ void mt_pll_init(void) ****************/ for (i = 0; i < APMIXED_NR_PLL; i++) { if (plls[i].rstb_shift != NO_RSTB_SHIFT) - setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); } /************** @@ -351,7 +351,7 @@ void mt_pll_init(void) ***************/ /* enable infrasys DCM */ - setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1); + setbits32(&mt8173_infracfg->top_dcmctl, 0x1); write32(&mtk_topckgen->clk_mode, 0x1); write32(&mtk_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */ @@ -374,16 +374,16 @@ void mt_pll_init(void) void mt_pll_enable_ssusb_clk(void) { /* set RG_LTECLKSQ_EN */ - setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1); + setbits32(&mtk_apmixed->ap_pll_con0, 0x1); udelay(100); /* wait for PLL stable */ /* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */ - setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1 << 1); - setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1); + setbits32(&mtk_apmixed->ap_pll_con0, 0x1 << 1); + setbits32(&mtk_apmixed->ap_pll_con2, 0x1); udelay(100); /* wait for PLL stable */ /* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */ - setbits_le32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); + setbits32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); } @@ -391,7 +391,7 @@ void mt_pll_enable_ssusb_clk(void) void mt_pll_post_init(void) { /* CPU clock divide by 1 */ - clrbits_le32(&mt8173_infracfg->top_ckdiv1, 0x3ff); + clrbits32(&mt8173_infracfg->top_ckdiv1, 0x3ff); /* select ARMPLL */ write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1); @@ -414,20 +414,20 @@ void mt_pll_set_aud_div(u32 rate) if (apll1) { /* mclk */ - clrbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5); - clrsetbits_le32(&mtk_topckgen->clk_auddiv_1, 0xff << 8, - mclk_div << 8); + clrbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); + clrsetbits32(&mtk_topckgen->clk_auddiv_1, 0xff << 8, + mclk_div << 8); /* bclk */ - clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 24, - 7 << 24); + clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 24, + 7 << 24); } else { /* mclk */ - setbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5); - clrsetbits_le32(&mtk_topckgen->clk_auddiv_2, 0xff << 8, - mclk_div << 8); + setbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); + clrsetbits32(&mtk_topckgen->clk_auddiv_2, 0xff << 8, + mclk_div << 8); /* bclk */ - clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 28, - 7 << 28); + clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 28, + 7 << 28); } } @@ -441,19 +441,19 @@ void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params) u32 mpll_sdm_pcw_20_0 = 0xF13B1; /* disable MPLL for adjusting memory clk frequency */ - clrbits_le32(&mtk_apmixed->mpll_con0, BIT(0)); + clrbits32(&mtk_apmixed->mpll_con0, BIT(0)); /* MPLL configuration: mode selection */ - setbits_le32(&mtk_apmixed->mpll_con0, BIT(16)); - clrbits_le32(&mtk_apmixed->mpll_con0, 0x7 << 4); - clrbits_le32(&mtk_apmixed->pll_test_con0, 1 << 31); + setbits32(&mtk_apmixed->mpll_con0, BIT(16)); + clrbits32(&mtk_apmixed->mpll_con0, 0x7 << 4); + clrbits32(&mtk_apmixed->pll_test_con0, 1 << 31); /* set RG_MPLL_SDM_PCW for feedback divide ratio */ - clrsetbits_le32(&mtk_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0); + clrsetbits32(&mtk_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0); } void mt_mem_pll_config_post(void) { /* power up sequence starts: enable MPLL */ - setbits_le32(&mtk_apmixed->mpll_con0, BIT(0)); + setbits32(&mtk_apmixed->mpll_con0, BIT(0)); } void mt_mem_pll_mux(void) diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index af88343c14f1..a15447c20f2c 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -170,11 +170,11 @@ s32 pwrap_init(void) s32 sub_return1 = 0; u16 rdata = 0x0; - setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + setbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* add 1us delay for toggling SW reset */ udelay(1); /* clear reset bit */ - clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + clrbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* Enable DCM */ write32(&mtk_pwrap->dcm_en, 3); diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index cf2ffa264bdf..1b0de79e3436 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -47,10 +47,10 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | - SPI_CFG1_TICK_DLY_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); + clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | + SPI_CFG1_TICK_DLY_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } static const struct spi_ctrlr spi_flash_ctrlr = { -- cgit v1.2.3