From 86b3bf10e60c137b01b81a37ce9827757f6af42d Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Fri, 19 Jun 2020 15:28:55 +0800 Subject: soc/mediatek: Add function to raise the CPU frequency of MT8192 Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq(). Implement mt_pll_raise_little_cpu_freq() in MT8192. Signed-off-by: Weiyi Lu Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8183/pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/mediatek/mt8183') diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 4570269421d0..0e96f4cc6807 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -362,7 +362,7 @@ void mt_pll_init(void) setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } -void mt_pll_raise_ca53_freq(u32 freq) +void mt_pll_raise_little_cpu_freq(u32 freq) { /* enable [4] intermediate clock armpll_divider_pll1_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); -- cgit v1.2.3