From 245fe4bd2933f43b9203f0c602bf59d3bf98ce21 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 28 Jul 2022 18:46:30 +0800 Subject: soc/mediatek: Move common definitions to dramc_soc_common.h Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8186/include/soc/dramc_soc.h | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) (limited to 'src/soc/mediatek/mt8186/include/soc') diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_soc.h b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h index 5602e144cbc9..ba768de119d2 100644 --- a/src/soc/mediatek/mt8186/include/soc/dramc_soc.h +++ b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h @@ -3,6 +3,8 @@ #ifndef __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ #define __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ +#include + typedef enum { CHANNEL_A = 0, CHANNEL_B, @@ -35,22 +37,6 @@ typedef enum { DRAM_DFS_SHUFFLE_MAX, } DRAM_DFS_SHUFFLE_TYPE_T; -/* - * Internal CBT mode enum - * 1. Calibration flow uses vGet_Dram_CBT_Mode to - * differentiate between mixed vs non-mixed LP4 - * 2. Declared as dram_cbt_mode[RANK_MAX] internally to - * store each rank's CBT mode type - */ -typedef enum { - CBT_NORMAL_MODE = 0, - CBT_BYTE_MODE1, -} DRAM_CBT_MODE_T; - #define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX -#define DQS_NUMBER_LP4 2 -#define DQS_BIT_NUMBER 8 -#define DQ_DATA_WIDTH_LP4 16 - #endif /* __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ */ -- cgit v1.2.3