From f371a78d907666afde4d945a56f9ca1e9c2152c8 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Tue, 21 Dec 2021 12:52:40 +0800 Subject: soc/medaitek/mt8195: adjust USB phy shift value There is a design issue of bit shift which will drop a bit for USB3 phy on MT8195. Therefore, we add this patch to set USB phy registers from value of efuse. BUG=b:211528577 TEST=build pass Signed-off-by: Rex-BC Chen Signed-off-by: Tianping Fang Tested-by: Tianping Fang Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8195/include/soc/usb.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'src/soc/mediatek/mt8195/include/soc') diff --git a/src/soc/mediatek/mt8195/include/soc/usb.h b/src/soc/mediatek/mt8195/include/soc/usb.h index e39ec3841d2b..c3b3c586f6a6 100644 --- a/src/soc/mediatek/mt8195/include/soc/usb.h +++ b/src/soc/mediatek/mt8195/include/soc/usb.h @@ -19,6 +19,21 @@ check_member(ssusb_sif_port, u3phya, 0x800); check_member(ssusb_sif_port, u3phya_da, 0x900); check_member(ssusb_sif_port, reserved2, 0xa00); -#define USB_PORT_NUMBER 1 +DEFINE_BIT(AUTO_LOAD_DIS, 12) +DEFINE_BITFIELD(TX_IMP_CAL, 28, 24) +DEFINE_BIT(TX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(RX_IMP_CAL, 28, 24) +DEFINE_BIT(RX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(INTR_CAL, 15, 10) + +#define TX_IMP_MASK 0x1F +#define TX_IMP_SHIFT 0 +#define RX_IMP_MASK 0x3E0 +#define RX_IMP_SHIFT 5 +#define INTR_CAL_MASK 0xFC00 +#define INTR_CAL_SHIFT 10 + +#define USB_PHY_SETTING_REG 0x11C10184 +#define USB_PORT_NUMBER 1 #endif -- cgit v1.2.3