From 44cff7a8975b2adbf2866718ec8c61ab0d9bd505 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 17 Aug 2018 15:38:59 +0800 Subject: cbtable: remove chromeos_acpi from cbtable Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/stoneyridge/include/soc/nvs.h | 2 +- src/soc/intel/apollolake/include/soc/nvs.h | 2 +- src/soc/intel/baytrail/include/soc/device_nvs.h | 3 --- src/soc/intel/baytrail/include/soc/nvs.h | 2 +- src/soc/intel/braswell/include/soc/device_nvs.h | 3 --- src/soc/intel/braswell/include/soc/nvs.h | 2 +- src/soc/intel/broadwell/include/soc/device_nvs.h | 3 --- src/soc/intel/broadwell/include/soc/nvs.h | 2 +- src/soc/intel/cannonlake/include/soc/nvs.h | 2 +- src/soc/intel/fsp_baytrail/include/soc/device_nvs.h | 3 --- src/soc/intel/skylake/include/soc/device_nvs.h | 3 --- src/soc/intel/skylake/include/soc/nvs.h | 2 +- 12 files changed, 7 insertions(+), 22 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index b4f7213eca6e..bcac3a9d8c09 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -55,6 +55,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif /* __SOC_STONEYRIDGE_NVS_H__ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index c7be979553b1..3250aeb27713 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -53,6 +53,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index b4fe65e7d9e8..bc6f7ec5de18 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -19,9 +19,6 @@ #include #include -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define LPSS_NVS_SIO_DMA1 0 #define LPSS_NVS_I2C1 1 #define LPSS_NVS_I2C2 2 diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 21cdb142a4db..715929d7ea15 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -102,7 +102,7 @@ typedef struct global_nvs_t { /* Baytrail LPSS (0x1000) */ device_nvs_t dev; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 268655e7cb00..8ed534eb9129 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -20,9 +20,6 @@ #include #include -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define LPSS_NVS_SIO_DMA1 0 #define LPSS_NVS_I2C1 1 #define LPSS_NVS_I2C2 2 diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 89a434bf8b7b..05831bb7d1a0 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -106,7 +106,7 @@ typedef struct global_nvs_t { /* LPSS (0x1000) */ device_nvs_t dev; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); #if ENV_SMM diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h index 15240d13b4b4..d17b3d461e9d 100644 --- a/src/soc/intel/broadwell/include/soc/device_nvs.h +++ b/src/soc/intel/broadwell/include/soc/device_nvs.h @@ -19,9 +19,6 @@ #include #include -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define SIO_NVS_DMA 0 #define SIO_NVS_I2C0 1 #define SIO_NVS_I2C1 2 diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 34673d55bc3a..2e51e1bd205d 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -94,7 +94,7 @@ typedef struct global_nvs_t { /* Device specific (0x1000) */ device_nvs_t dev; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h index 6c64f3ac2c05..1e5562566d63 100644 --- a/src/soc/intel/cannonlake/include/soc/nvs.h +++ b/src/soc/intel/cannonlake/include/soc/nvs.h @@ -46,7 +46,7 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h index 5bafea6fd038..8eff8cdb6fd5 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h @@ -19,9 +19,6 @@ #include #include -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define LPSS_NVS_SIO_DMA1 0 #define LPSS_NVS_I2C1 1 #define LPSS_NVS_I2C2 2 diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h index 02c9e6580980..2b7d1267fcd3 100644 --- a/src/soc/intel/skylake/include/soc/device_nvs.h +++ b/src/soc/intel/skylake/include/soc/device_nvs.h @@ -20,9 +20,6 @@ #include #include -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define SIO_NVS_I2C0 0 #define SIO_NVS_I2C1 1 #define SIO_NVS_I2C2 2 diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index bd3610e65477..53fdded8e969 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -102,6 +102,6 @@ typedef struct global_nvs_t { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif -- cgit v1.2.3