From ad12b4f4404f7c3473dcf85960efe3f8a016f22b Mon Sep 17 00:00:00 2001 From: "Chris.Wang" Date: Wed, 28 Dec 2022 17:07:48 +0800 Subject: soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger Reviewed-by: Jason Glenesk Tested-by: build bot (Jenkins) --- src/soc/amd/mendocino/chip.h | 3 +++ src/soc/amd/mendocino/fsp_m_params.c | 2 ++ 2 files changed, 5 insertions(+) (limited to 'src/soc') diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index c206445e5871..cf31cd7a30a4 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -164,6 +164,9 @@ struct soc_amd_mendocino_config { uint8_t usb_phy_custom; struct usb_phy_config usb_phy; + /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal + Integrity is highly recommended. */ + uint8_t dxio_tx_vboost_enable; }; #endif /* MENDOCINO_CHIP_H */ diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index d6eae9a7be69..8533743d514a 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -169,6 +169,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->usb_phy_ptr = 0; } + mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; + fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); mb_pre_fspm(mcfg); -- cgit v1.2.3