From dadcbfbe8c682c89b277fdbdfdd26cabd15fc20a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 4 Oct 2020 14:48:05 +0200 Subject: soc/intel: convert XTAL frequency constant to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/alderlake/Kconfig | 3 +++ src/soc/intel/alderlake/cpu.c | 12 +++++++----- src/soc/intel/alderlake/include/soc/cpu.h | 3 --- src/soc/intel/apollolake/Kconfig | 3 +++ src/soc/intel/apollolake/include/soc/cpu.h | 3 --- src/soc/intel/apollolake/pmutil.c | 12 +++++++----- src/soc/intel/cannonlake/Kconfig | 3 +++ src/soc/intel/cannonlake/cpu.c | 11 +++++++---- src/soc/intel/cannonlake/include/soc/cpu.h | 3 --- src/soc/intel/common/block/cpu/Kconfig | 5 +++++ src/soc/intel/elkhartlake/Kconfig | 3 +++ src/soc/intel/elkhartlake/cpu.c | 12 +++++++----- src/soc/intel/elkhartlake/include/soc/cpu.h | 3 --- src/soc/intel/icelake/Kconfig | 3 +++ src/soc/intel/icelake/cpu.c | 12 +++++++----- src/soc/intel/icelake/include/soc/cpu.h | 3 --- src/soc/intel/jasperlake/Kconfig | 3 +++ src/soc/intel/jasperlake/cpu.c | 12 +++++++----- src/soc/intel/jasperlake/include/soc/cpu.h | 3 --- src/soc/intel/skylake/Kconfig | 3 +++ src/soc/intel/skylake/cpu.c | 12 +++++++----- src/soc/intel/skylake/include/soc/cpu.h | 3 --- src/soc/intel/tigerlake/Kconfig | 3 +++ src/soc/intel/tigerlake/cpu.c | 12 +++++++----- src/soc/intel/tigerlake/include/soc/cpu.h | 3 --- 25 files changed, 85 insertions(+), 63 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index dc9e823f93b5..1a3f0724ae6c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -136,6 +136,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index ee8051d56842..e6a21c170e6d 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -111,15 +111,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 3c11183831ec..71c2f47605ad 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -19,7 +19,4 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index c1b5252aa8b4..69d42bdf19b0 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -157,6 +157,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 100 +config CPU_XTAL_HZ + default 19200000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 490820c3f67b..38b830a16f71 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -6,9 +6,6 @@ #include #include -/* Common Timer Copy (CTC) frequency - 19.2MHz. */ -#define CTC_FREQ 19200000 - struct device; void apollolake_init_cpus(struct device *dev); void mainboard_devtree_update(struct device *dev); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index c6d2eec791d9..e0de93eae4bb 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -180,15 +180,17 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dc2be28f8194..24f64b188726 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -245,6 +245,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 24000000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 216 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ddedb3fed231..062203421722 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -114,19 +114,22 @@ static void enable_pm_timer_emulation(void) { msr_t msr; + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); } + static void set_energy_perf_bias(u8 policy) { msr_t msr; diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index b356d3a9b877..3542a2b8a40d 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -22,9 +22,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 24MHz. */ -#define CTC_FREQ 24000000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9e95a8aa90a6..9023b58d54fe 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -99,6 +99,11 @@ config INTEL_TME it would get enabled. If CPU supports MKTME, this same config option enables MKTME. +config CPU_XTAL_HZ + int + help + Base clock which virtually everything runs on. + config CPU_SUPPORTS_PM_TIMER_EMULATION bool default n diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 40770d0172ca..05077ad31605 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -133,6 +133,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 382bbf7b01ee..271d244db969 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -105,15 +105,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/elkhartlake/include/soc/cpu.h b/src/soc/intel/elkhartlake/include/soc/cpu.h index 6ee34f234c30..ec3cd3ec019e 100644 --- a/src/soc/intel/elkhartlake/include/soc/cpu.h +++ b/src/soc/intel/elkhartlake/include/soc/cpu.h @@ -21,9 +21,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 027ed7ddf67a..21da528daa47 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -127,6 +127,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 2823fd7c4ea3..e76f61fa99ba 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -105,15 +105,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index a23133367e9f..5dc22ded7618 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -21,9 +21,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index ba7e62136caa..d5adc600bb1b 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -137,6 +137,9 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 +config CPU_XTAL_HZ + default 38400000 + config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 3 diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 3a50929a9b9d..1944e5c26901 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -105,15 +105,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h index c61f2ee95f38..40cebd4c0609 100644 --- a/src/soc/intel/jasperlake/include/soc/cpu.h +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -21,9 +21,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 14d4fa178134..55e74cd3606b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -241,6 +241,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 24000000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index f1b40f6d011f..5ec002322bc5 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -169,15 +169,17 @@ static void configure_c_states(void) */ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 740b3d3fb018..473068c2102f 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -25,9 +25,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 24MHz. */ -#define CTC_FREQ 24000000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 0021da5821da..2b5f0baeb1a5 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -138,6 +138,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index be056fb7a45b..1a5165d1e5d8 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -111,15 +111,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 47a41ebc9986..2d6336a9c431 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -21,7 +21,4 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #endif -- cgit v1.2.3