From fdb07582567414f9e93c5dc0c24b2dce63485b14 Mon Sep 17 00:00:00 2001 From: Fred Reitberger Date: Fri, 15 Jul 2022 08:05:56 -0400 Subject: soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM size Add static check to ensure the reserved APOB DRAM space is the same size as the MRC_CACHE region specified in the fmap. Update sabrina APOB DRAM size to match the fmap. TEST: Timeless builds identical. Test build with a larger MRC_CACHE than APOB DRAM failed the assert as expected. Signed-off-by: Fred Reitberger Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/apob/apob_cache.c | 3 +++ src/soc/amd/sabrina/Kconfig | 4 ++-- src/soc/amd/sabrina/root_complex.c | 4 ++-- 3 files changed, 7 insertions(+), 4 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index f20337734d29..32207bb59021 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -23,6 +23,9 @@ #error Incorrect APOB configuration setting(s) #endif +_Static_assert(CONFIG_PSP_APOB_DRAM_SIZE == DEFAULT_MRC_CACHE_SIZE, + "APOB DRAM reserved space != to MRC CACHE size - check your config"); + #define APOB_SIGNATURE 0x424F5041 /* 'APOB' */ /* APOB_BASE_HEADER from AGESA */ diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 62ae5989f9d6..997a1beadd1e 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -125,11 +125,11 @@ config PSP_APOB_DRAM_ADDRESS config PSP_APOB_DRAM_SIZE hex - default 0x20000 + default 0x1E000 config PSP_SHAREDMEM_BASE hex - default 0x2021000 if VBOOT + default 0x201F000 if VBOOT default 0x0 help This variable defines the base address in DRAM memory where PSP copies diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c index c911106e6b3a..99602e803be7 100644 --- a/src/soc/amd/sabrina/root_complex.c +++ b/src/soc/amd/sabrina/root_complex.c @@ -76,7 +76,7 @@ struct dptc_input { * | (C_ENV_BOOTBLOCK_SIZE) | * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | - * | (86KiB) | + * | (30KiB) | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 @@ -88,7 +88,7 @@ struct dptc_input { * | PSP shared (vboot workbuf) | * | (PSP_SHAREDMEM_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (128KiB) | + * | APOB (120KiB) | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS * | Early BSP stack | * | (EARLYRAM_BSP_STACK_SIZE) | -- cgit v1.2.3