From 9ed0df4c380dc56a81a59a104b1ccac19cd52c35 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 12 Oct 2019 14:18:18 +0200 Subject: sb/intel/i82801ix: Add common code to set up LPC IO decode ranges This does the following: - Add gen[1-4]_dec options to the devicetree to set up generic LPC decode ranges in the southbridge code. - Move setting up some default decode ranges to a common place. If somehow a board needs to override this behavior it can happen in the mb_setup_superio() hook (that will be renamed when moving to C_ENVIRONMENT_BOOTBLOCK). Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801ix/chip.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/southbridge/intel/i82801ix/chip.h') diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 0b3e0b5a5035..73ee822f7431 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -88,6 +88,12 @@ struct southbridge_intel_i82801ix_config { } pcie_power_limits[6]; uint8_t pcie_hotplug_map[8]; + + /* Additional LPC IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; }; #endif /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */ -- cgit v1.2.3