From 029d997b6eb0c784b844bf554dec5c33286b6507 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 23 Apr 2021 12:22:59 -0600 Subject: amd/cezanne: Add slow_ppt_time & thermctl_limit to UPD These values will be added in the upcoming STAPM configuration update. BUG=b:185209734 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3780259 Signed-off-by: Martin Roth Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648 Tested-by: build bot (Jenkins) Reviewed-by: Eric Peers Reviewed-by: chris wang Reviewed-by: Raul Rangel --- src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/vendorcode/amd') diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index dd59d52ac6e0..6e9a1f096930 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -65,7 +65,9 @@ typedef struct __packed { /** Offset 0x0405**/ uint8_t cppc_preferred_cores; /** Offset 0x0406**/ uint8_t stapm_boost; /** Offset 0x0407**/ uint32_t stapm_time_constant; - /** Offset 0x040B**/ uint8_t smu_soc_tuning_reserved[17]; + /** Offset 0x040B**/ uint32_t slow_ppt_time_constant; + /** Offset 0x040F**/ uint32_t thermctl_limit; + /** Offset 0x0413**/ uint8_t smu_soc_tuning_reserved[9]; /** Offset 0x041C**/ uint8_t iommu_support; /** Offset 0x041D**/ uint8_t pspp_policy; /** Offset 0x041E**/ uint8_t enable_nb_azalia; -- cgit v1.2.3