From dd4741c7bd2365156eaf267dedbbbc7cb86df465 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 22 Jan 2021 12:02:02 -0700 Subject: vendorcode/google/chromeos: Build CSE Board Reset in Romstage CSE Firmware Sync is being performed in romstage currently. But the CSE board reset is not included as part of romstage. This causes the CSE firmware sync to use global reset instead of EC assisted AP reset with the old Cr50 Firmware version. Include the board specific CSE reset in romstage. BUG=b:171731175,b:177795247 BRANCH=dedede,volteer,puff TEST=Ensured that the Drawlat boots to OS with both old(0.0.22) and new(0.6.7) Cr50 FW versions. Change-Id: I5e362271ffb68ffd5884279acd1ab0a462195a8a Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/49850 Reviewed-by: Evan Green Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/vendorcode/google/chromeos/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/vendorcode/google') diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index fb11e11c8d97..ba00d7778c60 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -10,6 +10,8 @@ ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c + +romstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c bootblock-y += watchdog.c -- cgit v1.2.3