From 01d75f4172e73fbcdc08ce0a13eaa0efb400ff12 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Thu, 30 Mar 2017 20:12:21 +0530 Subject: soc/intel/common/block: Add Intel common UART code Create Intel Common UART driver code. This code does below UART configuration for bootblock phase. * Program BAR * Configure reset register * Configure clock register Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/18952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- .../intel/common/block/include/intelblocks/uart.h | 24 +++++++++++++++ src/soc/intel/common/block/uart/Kconfig | 5 ++++ src/soc/intel/common/block/uart/Makefile.inc | 1 + src/soc/intel/common/block/uart/uart.c | 35 ++++++++++++++++++++++ 4 files changed, 65 insertions(+) create mode 100644 src/soc/intel/common/block/include/intelblocks/uart.h create mode 100644 src/soc/intel/common/block/uart/Kconfig create mode 100644 src/soc/intel/common/block/uart/Makefile.inc create mode 100644 src/soc/intel/common/block/uart/uart.c (limited to 'src') diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h new file mode 100644 index 000000000000..ed4c7f012734 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_UART_H +#define SOC_INTEL_COMMON_BLOCK_UART_H + +#include + +void uart_common_init(device_t dev, uintptr_t baseaddr, + uint32_t clk_m_val, uint32_t clk_n_val); + +#endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig new file mode 100644 index 000000000000..103659f4c4ed --- /dev/null +++ b/src/soc/intel/common/block/uart/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_UART + bool + select SOC_INTEL_COMMON_BLOCK_LPSS + help + Intel Processor common UART support diff --git a/src/soc/intel/common/block/uart/Makefile.inc b/src/soc/intel/common/block/uart/Makefile.inc new file mode 100644 index 000000000000..13f5da880f19 --- /dev/null +++ b/src/soc/intel/common/block/uart/Makefile.inc @@ -0,0 +1 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c \ No newline at end of file diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c new file mode 100644 index 000000000000..729a31ba1e29 --- /dev/null +++ b/src/soc/intel/common/block/uart/uart.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val, + uint32_t clk_n_val) +{ + /* Set UART base address */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); + + /* Enable memory access and bus master */ + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take UART out of reset */ + lpss_reset_release(baseaddr); + + /* Set M and N divisor inputs and enable clock */ + lpss_clk_update(baseaddr, clk_m_val, clk_n_val); +} -- cgit v1.2.3