From 3046948867ea060d59d7cad31c0718e3dc12c698 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 1 Aug 2022 17:37:46 +0200 Subject: soc/amd/sabrina/fch: enable XTAL pad disabling in S0i3 Switching off the pads of the internal crystal oscillator that connect to the crystal on the board in S0i3 saves a little power, so enable it. No measurements to quantify the power savings have been made. PPR #57243 revision 1.59 was used as a reference. BUG=b:237647468 TEST=None Signed-off-by: Felix Held Change-Id: I52f14ae5c614ad8ff0479b619de7164afa1e7648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66336 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Matt DeVillier --- src/soc/amd/sabrina/fch.c | 1 + src/soc/amd/sabrina/include/soc/southbridge.h | 1 + 2 files changed, 2 insertions(+) (limited to 'src') diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c index 533eb9489cfe..7368222338b3 100644 --- a/src/soc/amd/sabrina/fch.c +++ b/src/soc/amd/sabrina/fch.c @@ -178,6 +178,7 @@ static void cgpll_clock_gate_init(void) t = misc_read32(MISC_CLKGATEDCNTL); t |= ALINKCLK_GATEOFFEN; t |= BLINKCLK_GATEOFFEN; + t |= XTAL_PAD_S0I3_TURNOFF_EN; t |= XTAL_PAD_S3_TURNOFF_EN; t |= XTAL_PAD_S5_TURNOFF_EN; misc_write32(MISC_CLKGATEDCNTL, t); diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h index d72696285d36..789e73ff83e9 100644 --- a/src/soc/amd/sabrina/include/soc/southbridge.h +++ b/src/soc/amd/sabrina/include/soc/southbridge.h @@ -105,6 +105,7 @@ #define MISC_CLKGATEDCNTL 0x2c #define ALINKCLK_GATEOFFEN BIT(16) #define BLINKCLK_GATEOFFEN BIT(17) +#define XTAL_PAD_S0I3_TURNOFF_EN BIT(19) #define XTAL_PAD_S3_TURNOFF_EN BIT(20) #define XTAL_PAD_S5_TURNOFF_EN BIT(21) #define MISC_CGPLL_CONFIGURATION0 0x30 -- cgit v1.2.3