From 3ba59dc891b4618c50ba398c8395b575315b1442 Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Wed, 30 Jun 2021 01:30:16 -0700 Subject: mb/intel/ehlcrb: Update FIVR configs This patch sets the optimized FIVR configs for ehlcrb customized based on the performance measurements to achieve the better power savings in sleep states. - Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5 states. - Update the supported voltage states. - Update max supported current, voltage transition time and RFI spread spectrum. Signed-off-by: Lean Sheng Tan Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981 Reviewed-by: Angel Pons Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- .../intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src') diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 7c1d48aa148f..415c0c973ab8 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -140,6 +140,22 @@ chip soc/intel/elkhartlake [PchSerialIoIndexUART2] = 1, }" + register "fivr" = "{ + .fivr_config_en = true, + .v1p05_state = FIVR_ENABLE_ALL_SX, + .vnn_state = FIVR_ENABLE_ALL_SX, + .vnn_sx_state = FIVR_ENABLE_S3_S4_S5, + .v1p05_rail = FIVR_VOLTAGE_NORMAL, + .vnn_rail = FIVR_ENABLE_ALL_VOLTAGE, + .v1p05_icc_max_ma = 200, + .vnn_sx_mv = 1050, + .vcc_low_high_us = 12, + .vcc_ret_high_us = 54, + .vcc_ret_low_us = 43, + .vcc_off_high_us = 150, + .spread_spectrum = 15, + }" + # TSN GBE related UPDs register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" register "PchTsnGbeSgmiiEnable" = "1" -- cgit v1.2.3