From 87c42e870da871b8a866e07f5421a8711e988890 Mon Sep 17 00:00:00 2001
From: Varshit Pandya <pandyavarshit@gmail.com>
Date: Fri, 3 Nov 2023 16:55:52 +0530
Subject: soc/amd/genoa: Add mmio.asl

This patch adds asl code for MMIO device like I2C, UART, GPIO etc.

Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>t show
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78895
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/genoa/acpi/mmio.asl | 405 ++++++++++++++++++++++++++++++++++++++++
 src/soc/amd/genoa/acpi/soc.asl  |   2 +
 2 files changed, 407 insertions(+)
 create mode 100644 src/soc/amd/genoa/acpi/mmio.asl

(limited to 'src')

diff --git a/src/soc/amd/genoa/acpi/mmio.asl b/src/soc/amd/genoa/acpi/mmio.asl
new file mode 100644
index 000000000000..8ef61a7c19ec
--- /dev/null
+++ b/src/soc/amd/genoa/acpi/mmio.asl
@@ -0,0 +1,405 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/aoac.asl>
+#include <soc/aoac_defs.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <amdblocks/acpimmio_map.h>
+
+Device (AAHB)
+{
+	Name (_HID, "AAHB0000")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
+	})
+	Name (_STA, 0xb)
+}
+
+Device (GPIO)
+{
+	Name (_HID, GPIO_DEVICE_NAME)
+	Name (_CID, GPIO_DEVICE_NAME)
+	Name (_UID, 0)
+	Name (_DDN, GPIO_DEVICE_DESC)
+
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Level,
+				ActiveLow,
+				Shared, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IGPI
+		} Else {
+			IRQN = PGPI
+		}
+		If (IRQN == 0x1f || IRQN == 0) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR0)
+{
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA0
+		} Else {
+			IRQN = PUA0
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0)
+}
+
+Device (FUR1) {
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA1
+		} Else {
+			IRQN = PUA1
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_UART1, 0)
+}
+
+Device (FUR2) {
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA2
+		} Else {
+			IRQN = PUA2
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Name (STAT, 0x0)
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (STAT)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0)
+}
+
+Device (I2C0) {
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II20
+		} Else {
+			IRQN = PI20
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C0, 0)
+}
+
+Device (I2C1) {
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II21
+		} Else {
+			IRQN = PI21
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C1, 0)
+}
+
+Device (I2C2) {
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II22
+		} Else {
+			IRQN = PI22
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C2, 0)
+}
+
+Device (I2C3)
+{
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II23
+		} Else {
+			IRQN = PI23
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0)
+}
+
+Device (I2C4)
+{
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x4)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II24
+		} Else {
+			IRQN = PI24
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C4, 0)
+}
+
+Device (I2C5)
+{
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x5)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C5_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II25
+		} Else {
+			IRQN = PI25
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C5_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(FCH_AOAC_DEV_I2C5, 0)
+}
+
+Device (MISC)
+{
+	Name (_HID, "AMD0040")
+	Name (_UID, 0x3)
+	Name (_CRS, ResourceTemplate() {
+		Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
+	})
+	Name (_DSD, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package () { "is-rv", 1 },
+		},
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0B)
+	}
+}
diff --git a/src/soc/amd/genoa/acpi/soc.asl b/src/soc/amd/genoa/acpi/soc.asl
index 88b0df81c858..d7684cff09f5 100644
--- a/src/soc/amd/genoa/acpi/soc.asl
+++ b/src/soc/amd/genoa/acpi/soc.asl
@@ -3,4 +3,6 @@
 Scope(\_SB) {
 	/* global utility methods expected within the \_SB scope */
 	#include "pci_int_defs.asl"
+
+	#include "mmio.asl"
 } /* End \_SB scope */
-- 
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