From e9d9c1e89857498cf6cbcc9bb61283aadb665802 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 19 Apr 2023 10:08:36 +0200 Subject: vendorcode/mediatek/mt8195: Fix set but unused variables The clang compiler warns about this. Change-Id: I1584258aa24d6a0bf558b3c622bc53c156a37b09 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/74548 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas --- src/vendorcode/mediatek/mt8195/dramc/Hal_io.c | 4 -- .../mediatek/mt8195/dramc/dramc_actiming.c | 4 +- src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c | 4 +- .../mt8195/dramc/dramc_pi_calibration_api.c | 43 +++++++--------------- .../mediatek/mt8195/dramc/dramc_pi_main.c | 1 + src/vendorcode/mediatek/mt8195/dramc/emi.c | 3 -- .../mediatek/mt8195/include/dramc_common.h | 7 ++-- src/vendorcode/mediatek/mt8195/include/x_hal_io.h | 4 +- 8 files changed, 24 insertions(+), 46 deletions(-) (limited to 'src') diff --git a/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c b/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c index db551fef8afa..281c31957c64 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c +++ b/src/vendorcode/mediatek/mt8195/dramc/Hal_io.c @@ -501,7 +501,6 @@ void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32) { U8 ii, u1AllCount; U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM)); - U8 u1BCSupport = TRUE; reg32 &= 0xffff; @@ -512,7 +511,6 @@ void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32) reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL; if (u1AllCount > 1) u1AllCount >>= 1; - u1BCSupport = FALSE; } else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL) { @@ -551,7 +549,6 @@ void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32) U32 u4Val, u4RegTmp; U8 ii, u1AllCount; U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM)); - U8 u1BCSupport = TRUE; reg32 &= 0xffff; @@ -562,7 +559,6 @@ void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32) reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL; if (u1AllCount > 1) u1AllCount >>= 1; - u1BCSupport = FALSE; } else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL) { diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c index 5fa9bab3151b..6d88374fb420 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c @@ -131,7 +131,7 @@ static void DramcCalculate_Datlat_val(DRAMC_CTX_T *p) U32 u4TxPipeline = 0, u4RxPipeline = 0; U32 u4Datlat_dsel = 0, u4Datlat_margin = 1, u4RDSEL_Offset = 2; U32 u4DQ_P2S_Ratio = A_D->DQ_P2S_RATIO, u4CA_p2s_ratio = 0, u4CKR = A_D->CKR; - U32 u4CAdefault_delay = 1, u4CS2RL_start = 0, u4tRPRE_toggle = 0; + U32 u4CAdefault_delay = 1, u4CS2RL_start = 0; U32 u4DQSIEN_ser_latency = 0, u4CA_ser_latency = 0; U32 u4DQ_ui_unit = 0, u4CA_ui_unit = 0, u4Dram_ui_ratio = 2, u4MCK_unit = 0; U32 u4RL[2] = {0}, u4RLMax = 0, u4DQ_2_1stDVI4CK = 0, u4CA_MCKIO_ui_unit = 0; @@ -144,7 +144,6 @@ static void DramcCalculate_Datlat_val(DRAMC_CTX_T *p) if (u1IsLP4Family(p->dram_type)) { u4CS2RL_start = 7; - u4tRPRE_toggle = 0; u4tDQSCK_Max = 3500; u4RL[0] = Get_RL_by_MR_LP4(p->dram_cbt_mode[RANK_0], 0, LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency * 2)); u4RL[1] = Get_RL_by_MR_LP4(p->dram_cbt_mode[RANK_1], 0, LP4_DRAM_INIT_RLWL_MRfield_config(p->frequency * 2)); @@ -181,6 +180,7 @@ static void DramcCalculate_Datlat_val(DRAMC_CTX_T *p) u4MCK_unit = u4DQ_ui_unit * u4DQ_P2S_Ratio; u4CA_p2s_ratio = u4DQ_P2S_Ratio / u4CKR; u4DQSIEN_ser_latency = u1GetDQSIEN_p2s_latency(u4DQ_P2S_Ratio); + (void)u4DQSIEN_ser_latency; u4CA_ser_latency = u1GetDQ_CA_p2s_latency(u4CA_p2s_ratio, A_D->CA_FULL_RATE); u4CA_MCKIO_ui_unit = u4DQ_ui_unit * u4CKR / (A_D->CA_FULL_RATE + 1); u4RX_rdcmdout2rdcmdbus_by_ps = 3 * u4MCK_unit + u4CAdefault_delay * u4CA_ui_unit + u4CA_ser_latency * u4CA_MCKIO_ui_unit /*+ RX_C->ca_default_PI * RX_C->ca_MCKIO_ps / RX_C->ca_ui_pi_ratio*/ ; diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c index 7341ae3c0dde..81f7fdf773ed 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c @@ -1338,12 +1338,10 @@ static void TransferToSPMControl(DRAMC_CTX_T *p) #endif void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable) { - U32 val, fld; + U32 fld; fld = Fld(1, (Fld_shft(u4Field) + u1ShuIdx)); - val = (u1Enable) ? 1 : 0; - vIO32WriteFldAlign_All(u4Reg, u1Enable, fld); } diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index ff9fbdd7ec29..1a06e1e7a0c6 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -2443,7 +2443,7 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) //U32 uiCA, uiFinishCount, uiTemp; //S16 iDelay, pi_dly; //S32 iFirstPass_tmp[CATRAINING_NUM], iLastPass_tmp[CATRAINING_NUM]; - U32 uiCAWinSumMax; //uiCAWinSum, + //uiCAWinSum, U8 operating_fsp; U16 operation_frequency; //S32 iCA_PerBit_DelayLine[CATRAINING_NUM] = {0}, iCK_MIN = 1000 @@ -2466,9 +2466,8 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) S16 pi_step; //, pi_step_bk; S16 pi_start, pi_end; - u32 ca_ui, ca_ui_default; //, ca_ui_tmp + u32 ca_ui; //, ca_ui_tmp u32 ca_mck; //Vca_mck_tmp, a_mck_default - u32 ca_cmd0; u8 ca_pin_num; u8 step_respi = AUTOK_RESPI_1; //u32 capi_max; @@ -2573,9 +2572,9 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) #endif - ca_ui_default = ca_ui = get_ca_ui(p); + ca_ui = get_ca_ui(p); ca_mck = get_ca_mck(p); - ca_cmd0 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)); + u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)); vAutoRefreshSwitch(p, DISABLE); @@ -2591,9 +2590,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_TXRANKFIX); - - uiCAWinSumMax = 0; - operating_fsp = p->dram_fsp; operation_frequency = p->frequency; @@ -5628,6 +5624,7 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p, u1GatingErrorFlag=1; mcSHOW_ERR_MSG(("error, no all pass taps in DQS!,pass_byte_count=%d\n", pass_byte_count)); } + (void)u1GatingErrorFlag; #if (ENABLE_GATING_AUTOK_WA) @@ -6355,7 +6352,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, //U32 u1vrefidx; //U8 ucbit_first, ucbit_last; //S16 iDelay = 0, S16DelayBegin = 0, u4DelayStep=1; - U16 u16DelayStep = 1; //u16DelayEnd = 0 + //u16DelayEnd = 0 //U32 uiFinishCount; //U32 u4err_value, u4fail_bit, u4value; PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM]; //WinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM] @@ -6365,10 +6362,9 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, U16 u2FinalVref [DQS_BYTE_NUMBER]= {0xe, 0xe}; //u2VrefLevel U16 u2VrefBegin, u2VrefEnd, u2VrefStep; //U32 u4fail_bit_R, u4fail_bit_F; - U8 u1RXEyeScanEnable=(K_Type==NORMAL_K ? DISABLE : ENABLE),u1PrintCalibrationProc; + U8 u1RXEyeScanEnable=(K_Type==NORMAL_K ? DISABLE : ENABLE); //U16 u1min_bit_by_vref[DQS_BYTE_NUMBER], u1min_winsize_by_vref[DQS_BYTE_NUMBER]; //U16 u1min_bit[DQS_BYTE_NUMBER], u1min_winsize[DQS_BYTE_NUMBER]={0}; - U8 u1CalDQMNum = 0; //U32 u4PassFlags = 0xFFFF; U16 backup_RX_FinalVref_Value[DQS_BYTE_NUMBER]={0}; @@ -6411,14 +6407,12 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, #if (FEATURE_RDDQC_K_DMI == TRUE) if (u1UseTestEngine == PATTERN_RDDQC) { - u1CalDQMNum = 2; iDQMDlyPerbyte[0] = -0xFFFFFF; iDQMDlyPerbyte[1] = -0xFFFFFF; } else #endif { - u1CalDQMNum = 0; iDQMDlyPerbyte[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0); iDQMDlyPerbyte[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1); @@ -6528,8 +6522,6 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, #endif } - u1PrintCalibrationProc = ((u1VrefScanEnable == 0) || (u1RXEyeScanEnable == 1) || (u1AssignedVref != NULL)); - #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) { @@ -6599,7 +6591,9 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, else { u2VrefBegin = 0; + (void)u2VrefBegin; u2VrefEnd = EYESCAN_RX_VREF_RANGE_END-1; + (void)u2VrefEnd; //mcSHOW_DBG_MSG(("\nSet Eyescan Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd)); } #endif @@ -6626,11 +6620,9 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, u2VrefEnd = 0; u2VrefStep = 1; } + (void)u2VrefStep; - if (u1UseTestEngine == PATTERN_RDDQC) - u16DelayStep <<= 1; - #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) { @@ -7083,10 +7075,8 @@ static U8 aru1RxDatlatResult[RANK_MAX]; DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p) { //U8 ii, ucStartCalVal = 0; - U32 u4prv_register_080; //U32 u4err_value = 0xffffffff; - U8 ucfirst, ucbegin, ucsum, ucbest_step; //ucpipe_num = 0; - U16 u2DatlatBegin; + U8 ucbest_step; //ucpipe_num = 0; if (!p) @@ -7104,7 +7094,7 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p) mcSHOW_DBG_MSG(("[RxdatlatCal]\n")); - u4prv_register_080 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT)); + u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT)); vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAIL); @@ -7115,12 +7105,7 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p) //mcDUMP_REG_MSG(("DATLAT Default: 0x%x\n", ucbest_step)); - ucfirst = 0xff; - ucbegin = 0; - ucsum = 0; - DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); - u2DatlatBegin = 0; #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT) if (p->femmc_Ready == 1) @@ -9202,9 +9187,6 @@ void DramcTxOECalibration(DRAMC_CTX_T *p) //U8 ucdq_ui_large_reg_value=0xff, ucdq_ui_small_reg_value=0xff; //U8 ucdq_final_dqm_oen_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_final_dqm_oen_ui_small[DQS_BYTE_NUMBER] = {0}; //DRAM_STATUS_T KResult; - U8 u1TxDQOEShift = 0; - - u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4; //mcDUMP_REG_MSG(("\n[dumpRG] DramcTXOECalibration\n")); #if VENDER_JV_LOG @@ -9670,6 +9652,7 @@ static void DramcJmeterCalib(DRAMC_CTX_T *p, JMETER_T *pJmtrInfo, U16 u2JmDlySte U8 check; check = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), MISC_DUTYSCAN1_EYESCAN_DQS_OPT); + (void)check; for (ucdqs_dly = u2Jm_dly_start; ucdqs_dly < u2Jm_dly_end; ucdqs_dly += u2Jm_dly_step) { diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index e3baf7bba2d7..311939d1d52c 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -151,6 +151,7 @@ void vSetVcoreByFreq(DRAMC_CTX_T *p) //int ret; vio18 = vcore = vdram = vddq = vmddr = 0; + (void)vio18; #if __ETT__ hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq, &vmddr); diff --git a/src/vendorcode/mediatek/mt8195/dramc/emi.c b/src/vendorcode/mediatek/mt8195/dramc/emi.c index 5a1f09de5082..6a9321cfbc2e 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/emi.c +++ b/src/vendorcode/mediatek/mt8195/dramc/emi.c @@ -673,9 +673,6 @@ void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK]) unsigned long long ch0_rank0_size, ch0_rank1_size; unsigned long long ch1_rank0_size, ch1_rank1_size; unsigned int cen_emi_conh = mt_emi_sync_read(EMI_CONH); - unsigned long long dq_width; - - dq_width = 2; dram_rank_size[0] = 0; dram_rank_size[1] = 0; diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_common.h b/src/vendorcode/mediatek/mt8195/include/dramc_common.h index 0da3525c4b1d..393612c77d7a 100644 --- a/src/vendorcode/mediatek/mt8195/include/dramc_common.h +++ b/src/vendorcode/mediatek/mt8195/include/dramc_common.h @@ -73,6 +73,7 @@ /* mcSHOW_DBG_MSG3: Medium Low */ /* mcSHOW_DBG_MSG4: Low */ /**********************************************/ + #if __FLASH_TOOL_DA__ #define printf DBG_MSG #define print DBG_MSG @@ -246,10 +247,10 @@ #define mcSHOW_TIME_MSG(_x_) #define mcSHOW_ERR_MSG(_x_) {print _x_;} #else - #define mcSHOW_DBG_MSG(_x_) - #define mcSHOW_DBG_MSG2(_x_) + #define mcSHOW_DBG_MSG(_x_) { if (0) { print _x_; } } + #define mcSHOW_DBG_MSG2(_x_) { if (0) { print _x_; } } #define mcSHOW_DBG_MSG3(_x_) - #define mcSHOW_DBG_MSG4(_x_) + #define mcSHOW_DBG_MSG4(_x_) { if (0) { print _x_; } } #define mcSHOW_DBG_MSG5(_x_) #define mcSHOW_DBG_MSG6(_x_) #define mcSHOW_JV_LOG_MSG(_x_) diff --git a/src/vendorcode/mediatek/mt8195/include/x_hal_io.h b/src/vendorcode/mediatek/mt8195/include/x_hal_io.h index 5989ec8b9f57..184dd7a7a058 100644 --- a/src/vendorcode/mediatek/mt8195/include/x_hal_io.h +++ b/src/vendorcode/mediatek/mt8195/include/x_hal_io.h @@ -46,7 +46,7 @@ extern void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32 extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32); // ========================= -// public Macro for general use. +// public Macro for general use. //========================== #define u4IO32Read4B(reg32) u4Dram_Register_Read(p, reg32) #define vIO32Write4B(reg32, val32) ucDram_Register_Write(p, reg32, val32) @@ -65,6 +65,7 @@ extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32); UINT16 upk = 1; \ INT32 msk = (INT32)(list); \ { upk = 0; \ + (void)upk; \ ((U32)msk == 0xffffffff)? (vIO32Write4B(reg32, (list))): (((U32)msk)? vIO32Write4BMsk(reg32, (list), ((U32)msk)):(U32)0); \ } \ }/*lint -restore */ @@ -80,6 +81,7 @@ extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32); UINT16 upk = 1; \ INT32 msk = (INT32)(list); \ { upk = 0; \ + (void)upk; \ ((U32)msk == 0xffffffff)? (vIO32Write4B_All(reg32, (list))): (((U32)msk)? vIO32Write4BMsk_All(reg32, (list), ((U32)msk)): (void)0); \ } \ }/*lint -restore */ -- cgit v1.2.3