From ec098b5e7f3546356bdd3a215711745c336bd3d8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 23 Feb 2021 12:36:16 +0100 Subject: soc/amd: only print CPU family and model in bootblock Printing this in both bootblock and romstage is redundant, since the CPU family and model aren't expected to change between bootblock and romstage entry. Signed-off-by: Felix Held Reported-by: Paul Menzel Change-Id: Id7c6aea0d8a6dac39114593584e534661faea89d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51062 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/romstage.c | 3 --- src/soc/amd/picasso/romstage.c | 2 -- 2 files changed, 5 deletions(-) (limited to 'src') diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 773c6a97d5aa..2740d8c74cd4 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -29,9 +29,6 @@ asmlinkage void car_stage_entry(void) post_code(0x41); - u32 val = cpuid_eax(1); - printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - fsp_memory_init(acpi_is_wakeup_s3()); memmap_stash_early_dram_usage(); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index aa8da1ea6976..c085a5355fd5 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -147,8 +147,6 @@ asmlinkage void car_stage_entry(void) console_init(); post_code(0x42); - u32 val = cpuid_eax(1); - printk(BIOS_DEBUG, "Family_Model: %08x\n", val); /* Snapshot chipset state prior to any FSP call. */ fill_chipset_state(); -- cgit v1.2.3