From f3e5f9966f2598e51f52e8d06c543958327a7913 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Fri, 29 Jul 2022 10:10:44 +0800 Subject: mb/google/brya/variants/agah: set tcc_offset to 3 Set tcc_offset value to 3 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:240600260 TEST=emerge-draco coreboot verified by thermal team Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Sumeet R Pawnikar --- src/mainboard/google/brya/variants/agah/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index ae6ad4a22dd9..c459e034f32a 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -39,6 +39,7 @@ chip soc/intel/alderlake }, }" + register "tcc_offset" = "3" # TCC of 97 register "sagv" = "SaGv_Disabled" register "tcss_aux_ori" = "0x10" register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" -- cgit v1.2.3