From 7e241bff1883eba2b904cac06497670fd3440953 Mon Sep 17 00:00:00 2001
From: Martin Roth <martinroth@chromium.org>
Date: Wed, 21 Apr 2021 16:23:32 -0600
Subject: util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config

The revision B version of the MT53E1G32D2NP-046 memory chip will be used
in the next guybrush build.  It has a different internal layout than the
Revision A part, with 2 ZQ lines per module instead of 1.

BUG=b:186027256
TEST=Build only

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I066f40eb890648a9be17cfe0cee20d299000c11a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'util/spd_tools')

diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
index 2cc1fa49b824..3e6eb8bd49c9 100644
--- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt
@@ -60,6 +60,18 @@
                 "speedMbps": 4267
             }
         },
+        {
+            "name": "MT53E1G32D2NP-046 WT:B",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+        },
         {
             "name": "H9HKNNNCRMBVAR-NEH",
             "attribs": {
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