/* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ #include #include #include #include #include #include #include void amd_initcpuio(void) { UINT64 MsrReg; UINT32 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* The platform BIOS needs to ensure the memory ranges of Hudson legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * set to non-posted regions. */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); /* last address before processor local APIC at FEE00000 */ PciData = 0x00FEDF00; /* set NP (non-posted) bit */ PciData |= 1 << 7; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); /* lowest NP address is HPET at FED00000 */ PciData = (0xFED00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); /* last address before non-posted range */ PciData = 0x00FECF00; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Send all IO (0000-FFFF) to southbridge. */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); }